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target/i386: Trivial code motion and code style fix

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A new pair of braces has to be added to declare variables in the case block.
The code style is also fixed according to the transalte.c itself during the
code motion.

Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com>
Message-Id: <20210530150112.74411-1-ziqiaokong@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Ziqiao Kong 2021-05-30 23:01:12 +08:00 committed by Richard Henderson
parent 080ac33542
commit 505910a6e2
1 changed files with 472 additions and 461 deletions
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29
target/i386/tcg/translate.c
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@ -5919,6 +5919,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
/************************/ /************************/
/* floats */ /* floats */
case 0xd8 ... 0xdf: case 0xd8 ... 0xdf:
{
if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
/* if CR0.EM or CR0.TS are set, generate an FPU exception */ /* if CR0.EM or CR0.TS are set, generate an FPU exception */
/* XXX: what to do if illegal op ? */ /* XXX: what to do if illegal op ? */
@ -6050,13 +6051,15 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
s->mem_index, MO_LEUW); s->mem_index, MO_LEUW);
break; break;
} }
if ((op & 7) == 3) if ((op & 7) == 3) {
gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env);
}
break; break;
} }
break; break;
case 0x0c: /* fldenv mem */ case 0x0c: /* fldenv mem */
gen_helper_fldenv(cpu_env, s->A0, tcg_const_i32(dflag - 1)); gen_helper_fldenv(cpu_env, s->A0,
tcg_const_i32(dflag - 1));
break; break;
case 0x0d: /* fldcw mem */ case 0x0d: /* fldcw mem */
tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0, tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
@ -6064,7 +6067,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
gen_helper_fldcw(cpu_env, s->tmp2_i32); gen_helper_fldcw(cpu_env, s->tmp2_i32);
break; break;
case 0x0e: /* fnstenv mem */ case 0x0e: /* fnstenv mem */
gen_helper_fstenv(cpu_env, s->A0, tcg_const_i32(dflag - 1)); gen_helper_fstenv(cpu_env, s->A0,
tcg_const_i32(dflag - 1));
break; break;
case 0x0f: /* fnstcw mem */ case 0x0f: /* fnstcw mem */
gen_helper_fnstcw(s->tmp2_i32, cpu_env); gen_helper_fnstcw(s->tmp2_i32, cpu_env);
@ -6079,10 +6083,12 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env);
break; break;
case 0x2c: /* frstor mem */ case 0x2c: /* frstor mem */
gen_helper_frstor(cpu_env, s->A0, tcg_const_i32(dflag - 1)); gen_helper_frstor(cpu_env, s->A0,
tcg_const_i32(dflag - 1));
break; break;
case 0x2e: /* fnsave mem */ case 0x2e: /* fnsave mem */
gen_helper_fsave(cpu_env, s->A0, tcg_const_i32(dflag - 1)); gen_helper_fsave(cpu_env, s->A0,
tcg_const_i32(dflag - 1));
break; break;
case 0x2f: /* fnstsw mem */ case 0x2f: /* fnstsw mem */
gen_helper_fnstsw(s->tmp2_i32, cpu_env); gen_helper_fnstsw(s->tmp2_i32, cpu_env);
@ -6097,12 +6103,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env);
break; break;
case 0x3d: /* fildll */ case 0x3d: /* fildll */
tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEQ); tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEQ);
gen_helper_fildll_ST0(cpu_env, s->tmp1_i64); gen_helper_fildll_ST0(cpu_env, s->tmp1_i64);
break; break;
case 0x3f: /* fistpll */ case 0x3f: /* fistpll */
gen_helper_fistll_ST0(s->tmp1_i64, cpu_env); gen_helper_fistll_ST0(s->tmp1_i64, cpu_env);
tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEQ); tcg_gen_qemu_st_i64(s->tmp1_i64, s->A0,
s->mem_index, MO_LEQ);
gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env);
break; break;
default: default:
@ -6255,10 +6263,12 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
op1 = op & 7; op1 = op & 7;
if (op >= 0x20) { if (op >= 0x20) {
gen_helper_fp_arith_STN_ST0(op1, opreg); gen_helper_fp_arith_STN_ST0(op1, opreg);
if (op >= 0x30) if (op >= 0x30) {
gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env);
}
} else { } else {
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); gen_helper_fmov_FT0_STN(cpu_env,
tcg_const_i32(opreg));
gen_helper_fp_arith_ST0_FT0(op1); gen_helper_fp_arith_ST0_FT0(op1);
} }
} }
@ -6418,6 +6428,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
goto unknown_op; goto unknown_op;
} }
} }
}
break; break;
/************************/ /************************/
/* string ops */ /* string ops */