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target-arm queue:

Browse Source 
* Deprecate pxa2xx CPUs, iwMMXt emulation, -old-param option
  * Drop unused AArch64DecodeTable typedefs
  * Minor code cleanups
  * hw/net/cadence_gem:  Fix the mask/compare/disable-mask logic
  * linux-user: Do not define struct sched_attr if libc headers do
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Merge tag 'pull-target-arm-20250210' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Deprecate pxa2xx CPUs, iwMMXt emulation, -old-param option
 * Drop unused AArch64DecodeTable typedefs
 * Minor code cleanups
 * hw/net/cadence_gem:  Fix the mask/compare/disable-mask logic
 * linux-user: Do not define struct sched_attr if libc headers do

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 # gpg: Signature made Mon 10 Feb 2025 10:49:15 EST
 # gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
 # gpg:                issuer "peter.maydell@linaro.org"
 # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
 # gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
 # gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
 # gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
 # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20250210' of https://git.linaro.org/people/pmaydell/qemu-arm:
  linux-user: Do not define struct sched_attr if libc headers do
  qemu-options: Deprecate -old-param command line option
  hw/net/cadence_gem:  Fix the mask/compare/disable-mask logic
  hw/cpu/arm: Declare CPU QOM types using DEFINE_TYPES() macro
  hw/cpu/arm: Alias 'num-cpu' property on TYPE_REALVIEW_MPCORE
  hw/arm/fsl-imx7: Add local 'mpcore/gic' variables
  hw/arm/fsl-imx6ul: Add local 'mpcore/gic' variables
  hw/arm/fsl-imx6: Add local 'mpcore/gic' variables
  hw/arm/boot: Propagate vCPU to arm_load_dtb()
  target/arm: Drop unused AArch64DecodeTable typedefs
  tests/tcg/arm: Remove test-arm-iwmmxt test
  target/arm: deprecate the pxa2xx CPUs and iwMMXt emulation

Conflicts:
- The iwMMXt deprecation notice conflicted with the 32-bit host
  operating system deprecation notice. Add both notices.

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2025-02-10 13:22:07 -05:00
commit 4f1d018512
21 changed files with 205 additions and 249 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
docs/about/deprecated.rst
View File

@ -68,6 +68,19 @@ configurations (e.g. -smp drawers=1,books=1,clusters=1 for x86 PC machine) is
marked deprecated since 9.0, users have to ensure that all the topology members marked deprecated since 9.0, users have to ensure that all the topology members
described with -smp are supported by the target machine. described with -smp are supported by the target machine.
``-old-param`` option for booting Arm kernels via param_struct (since 10.0)
'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
The ``-old-param`` command line option is specific to Arm targets:
it is used when directly booting a guest kernel to pass it the
command line and other information via the old ``param_struct`` ABI,
rather than the newer ATAGS or DTB mechanisms. This option was only
ever needed to support ancient kernels on some old board types
like the ``akita`` or ``terrier``; it has been deprecated in the
kernel since 2001. None of the board types QEMU supports need
``param_struct`` support, so this option has been deprecated and will
be removed in a future QEMU version.
User-mode emulator command line arguments User-mode emulator command line arguments
----------------------------------------- -----------------------------------------
@ -211,6 +224,27 @@ Keeping 32-bit host support alive is a substantial burden for the
QEMU project. Thus QEMU will in future drop the support for all QEMU project. Thus QEMU will in future drop the support for all
32-bit host systems. 32-bit host systems.
linux-user mode CPUs
--------------------
iwMMXt emulation and the ``pxa`` CPUs (since 10.0)
''''''''''''''''''''''''''''''''''''''''''''''''''
The ``pxa`` CPU family (``pxa250``, ``pxa255``, ``pxa260``,
``pxa261``, ``pxa262``, ``pxa270-a0``, ``pxa270-a1``, ``pxa270``,
``pxa270-b0``, ``pxa270-b1``, ``pxa270-c0``, ``pxa270-c5``) are no
longer used in system emulation, because all the machine types which
used these CPUs were removed in the QEMU 9.2 release. These CPUs can
now only be used in linux-user mode, and to do that you would have to
explicitly select one of these CPUs with the ``-cpu`` command line
option or the ``QEMU_CPU`` environment variable.
We don't believe that anybody is using the iwMMXt emulation, and we do
not have any tests to validate it or any real hardware or similar
known-good implementation to test against. GCC is in the process of
dropping their support for iwMMXt codegen. These CPU types are
therefore deprecated in QEMU, and will be removed in a future release.
System emulator CPUs System emulator CPUs
-------------------- --------------------

11
hw/arm/boot.c
View File

@ -432,13 +432,12 @@ out:
return ret; return ret;
} }
static void fdt_add_psci_node(void *fdt) static void fdt_add_psci_node(void *fdt, ARMCPU *armcpu)
{ {
uint32_t cpu_suspend_fn; uint32_t cpu_suspend_fn;
uint32_t cpu_off_fn; uint32_t cpu_off_fn;
uint32_t cpu_on_fn; uint32_t cpu_on_fn;
uint32_t migrate_fn; uint32_t migrate_fn;
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
const char *psci_method; const char *psci_method;
int64_t psci_conduit; int64_t psci_conduit;
int rc; int rc;
@ -512,7 +511,8 @@ static void fdt_add_psci_node(void *fdt)
} }
int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
hwaddr addr_limit, AddressSpace *as, MachineState *ms) hwaddr addr_limit, AddressSpace *as, MachineState *ms,
ARMCPU *cpu)
{ {
void *fdt = NULL; void *fdt = NULL;
int size, rc, n = 0; int size, rc, n = 0;
@ -655,7 +655,7 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
} }
} }
fdt_add_psci_node(fdt); fdt_add_psci_node(fdt, cpu);
if (binfo->modify_dtb) { if (binfo->modify_dtb) {
binfo->modify_dtb(binfo, fdt); binfo->modify_dtb(binfo, fdt);
@ -1327,7 +1327,8 @@ void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
* decided whether to enable PSCI and set the psci-conduit CPU properties. * decided whether to enable PSCI and set the psci-conduit CPU properties.
*/ */
if (!info->skip_dtb_autoload && have_dtb(info)) { if (!info->skip_dtb_autoload && have_dtb(info)) {
if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { if (arm_load_dtb(info->dtb_start, info, info->dtb_limit,
as, ms, cpu) < 0) {
exit(1); exit(1);
} }
} }

52
hw/arm/fsl-imx6.c
View File

@ -117,6 +117,8 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
uint16_t i; uint16_t i;
qemu_irq irq; qemu_irq irq;
unsigned int smp_cpus = ms->smp.cpus; unsigned int smp_cpus = ms->smp.cpus;
DeviceState *mpcore = DEVICE(&s->a9mpcore);
DeviceState *gic;
if (smp_cpus > FSL_IMX6_NUM_CPUS) { if (smp_cpus > FSL_IMX6_NUM_CPUS) {
error_setg(errp, "%s: Only %d CPUs are supported (%d requested)", error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
@ -143,21 +145,21 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
} }
} }
object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", smp_cpus, object_property_set_int(OBJECT(mpcore), "num-cpu", smp_cpus, &error_abort);
&error_abort);
object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", object_property_set_int(OBJECT(mpcore), "num-irq",
FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort); FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), errp)) { if (!sysbus_realize(SYS_BUS_DEVICE(mpcore), errp)) {
return; return;
} }
sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX6_A9MPCORE_ADDR);
gic = mpcore;
for (i = 0; i < smp_cpus; i++) { for (i = 0; i < smp_cpus; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, sysbus_connect_irq(SYS_BUS_DEVICE(gic), i,
qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus, sysbus_connect_irq(SYS_BUS_DEVICE(gic), i + smp_cpus,
qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
} }
@ -195,8 +197,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr); sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore), qdev_get_gpio_in(gic, serial_table[i].irq));
serial_table[i].irq));
} }
s->gpt.ccm = IMX_CCM(&s->ccm); s->gpt.ccm = IMX_CCM(&s->ccm);
@ -207,8 +208,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR); sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore), qdev_get_gpio_in(gic, FSL_IMX6_GPT_IRQ));
FSL_IMX6_GPT_IRQ));
/* Initialize all EPIT timers */ /* Initialize all EPIT timers */
for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) { for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
@ -228,8 +228,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr); sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore), qdev_get_gpio_in(gic, epit_table[i].irq));
epit_table[i].irq));
} }
/* Initialize all I2C */ /* Initialize all I2C */
@ -249,8 +248,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr); sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore), qdev_get_gpio_in(gic, i2c_table[i].irq));
i2c_table[i].irq));
} }
/* Initialize all GPIOs */ /* Initialize all GPIOs */
@ -307,11 +305,9 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore), qdev_get_gpio_in(gic, gpio_table[i].irq_low));
gpio_table[i].irq_low));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
qdev_get_gpio_in(DEVICE(&s->a9mpcore), qdev_get_gpio_in(gic, gpio_table[i].irq_high));
gpio_table[i].irq_high));
} }
/* Initialize all SDHC */ /* Initialize all SDHC */
@ -338,8 +334,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
} }
sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr); sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore), qdev_get_gpio_in(gic, esdhc_table[i].irq));
esdhc_table[i].irq));
} }
/* USB */ /* USB */
@ -360,8 +355,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
FSL_IMX6_USBOH3_USB_ADDR + i * 0x200); FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore), qdev_get_gpio_in(gic, FSL_IMX6_USBn_IRQ[i]));
FSL_IMX6_USBn_IRQ[i]));
} }
/* Initialize all ECSPI */ /* Initialize all ECSPI */
@ -384,8 +378,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore), qdev_get_gpio_in(gic, spi_table[i].irq));
spi_table[i].irq));
} }
object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num, object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num,
@ -396,11 +389,9 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
} }
sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR); sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore), qdev_get_gpio_in(gic, FSL_IMX6_ENET_MAC_IRQ));
FSL_IMX6_ENET_MAC_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1, sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1,
qdev_get_gpio_in(DEVICE(&s->a9mpcore), qdev_get_gpio_in(gic, FSL_IMX6_ENET_MAC_1588_IRQ));
FSL_IMX6_ENET_MAC_1588_IRQ));
/* /*
* SNVS * SNVS
@ -427,8 +418,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]); sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a9mpcore), qdev_get_gpio_in(gic, FSL_IMX6_WDOGn_IRQ[i]));
FSL_IMX6_WDOGn_IRQ[i]));
} }
/* /*

64
hw/arm/fsl-imx6ul.c
View File

@ -157,10 +157,12 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
{ {
MachineState *ms = MACHINE(qdev_get_machine()); MachineState *ms = MACHINE(qdev_get_machine());
FslIMX6ULState *s = FSL_IMX6UL(dev); FslIMX6ULState *s = FSL_IMX6UL(dev);
DeviceState *mpcore = DEVICE(&s->a7mpcore);
int i; int i;
char name[NAME_SIZE]; char name[NAME_SIZE];
SysBusDevice *sbd; DeviceState *gic;
DeviceState *d; SysBusDevice *gicsbd;
DeviceState *cpu;
if (ms->smp.cpus > 1) { if (ms->smp.cpus > 1) {
error_setg(errp, "%s: Only a single CPU is supported (%d requested)", error_setg(errp, "%s: Only a single CPU is supported (%d requested)",
@ -173,19 +175,19 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
/* /*
* A7MPCORE * A7MPCORE
*/ */
object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", 1, &error_abort); object_property_set_int(OBJECT(mpcore), "num-cpu", 1, &error_abort);
object_property_set_int(OBJECT(&s->a7mpcore), "num-irq", object_property_set_int(OBJECT(mpcore), "num-irq",
FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, &error_abort); FSL_IMX6UL_MAX_IRQ + GIC_INTERNAL, &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); sysbus_realize(SYS_BUS_DEVICE(mpcore), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR); sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX6UL_A7MPCORE_ADDR);
sbd = SYS_BUS_DEVICE(&s->a7mpcore); gic = mpcore;
d = DEVICE(&s->cpu); gicsbd = SYS_BUS_DEVICE(gic);
cpu = DEVICE(&s->cpu);
sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(d, ARM_CPU_IRQ)); sysbus_connect_irq(gicsbd, 0, qdev_get_gpio_in(cpu, ARM_CPU_IRQ));
sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(d, ARM_CPU_FIQ)); sysbus_connect_irq(gicsbd, 1, qdev_get_gpio_in(cpu, ARM_CPU_FIQ));
sysbus_connect_irq(sbd, 2, qdev_get_gpio_in(d, ARM_CPU_VIRQ)); sysbus_connect_irq(gicsbd, 2, qdev_get_gpio_in(cpu, ARM_CPU_VIRQ));
sysbus_connect_irq(sbd, 3, qdev_get_gpio_in(d, ARM_CPU_VFIQ)); sysbus_connect_irq(gicsbd, 3, qdev_get_gpio_in(cpu, ARM_CPU_VFIQ));
/* /*
* A7MPCORE DAP * A7MPCORE DAP
@ -244,8 +246,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_GPTn_ADDR[i]); FSL_IMX6UL_GPTn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX6UL_GPTn_IRQ[i]));
FSL_IMX6UL_GPTn_IRQ[i]));
} }
/* /*
@ -269,8 +270,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_EPITn_ADDR[i]); FSL_IMX6UL_EPITn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX6UL_EPITn_IRQ[i]));
FSL_IMX6UL_EPITn_IRQ[i]));
} }
/* /*
@ -307,12 +307,10 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_GPIOn_ADDR[i]); FSL_IMX6UL_GPIOn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX6UL_GPIOn_LOW_IRQ[i]));
FSL_IMX6UL_GPIOn_LOW_IRQ[i]));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX6UL_GPIOn_HIGH_IRQ[i]));
FSL_IMX6UL_GPIOn_HIGH_IRQ[i]));
} }
/* /*
@ -366,8 +364,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_SPIn_ADDR[i]); FSL_IMX6UL_SPIn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX6UL_SPIn_IRQ[i]));
FSL_IMX6UL_SPIn_IRQ[i]));
} }
/* /*
@ -392,8 +389,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]); sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX6UL_I2Cn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX6UL_I2Cn_IRQ[i]));
FSL_IMX6UL_I2Cn_IRQ[i]));
} }
/* /*
@ -430,8 +426,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_UARTn_ADDR[i]); FSL_IMX6UL_UARTn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX6UL_UARTn_IRQ[i]));
FSL_IMX6UL_UARTn_IRQ[i]));
} }
/* /*
@ -480,12 +475,10 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_ENETn_ADDR[i]); FSL_IMX6UL_ENETn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX6UL_ENETn_IRQ[i]));
FSL_IMX6UL_ENETn_IRQ[i]));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
FSL_IMX6UL_ENETn_TIMER_IRQ[i]));
} }
/* /*
@ -521,8 +514,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
FSL_IMX6UL_USB02_USBn_ADDR[i]); FSL_IMX6UL_USB02_USBn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX6UL_USBn_IRQ[i]));
FSL_IMX6UL_USBn_IRQ[i]));
} }
/* /*
@ -547,8 +539,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_USDHCn_ADDR[i]); FSL_IMX6UL_USDHCn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX6UL_USDHCn_IRQ[i]));
FSL_IMX6UL_USDHCn_IRQ[i]));
} }
/* /*
@ -580,8 +571,7 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
FSL_IMX6UL_WDOGn_ADDR[i]); FSL_IMX6UL_WDOGn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX6UL_WDOGn_IRQ[i]));
FSL_IMX6UL_WDOGn_IRQ[i]));
} }
/* /*

52
hw/arm/fsl-imx7.c
View File

@ -166,7 +166,8 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
{ {
MachineState *ms = MACHINE(qdev_get_machine()); MachineState *ms = MACHINE(qdev_get_machine());
FslIMX7State *s = FSL_IMX7(dev); FslIMX7State *s = FSL_IMX7(dev);
Object *o; DeviceState *mpcore = DEVICE(&s->a7mpcore);
DeviceState *gic;
int i; int i;
qemu_irq irq; qemu_irq irq;
char name[NAME_SIZE]; char name[NAME_SIZE];
@ -182,7 +183,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
* CPUs * CPUs
*/ */
for (i = 0; i < smp_cpus; i++) { for (i = 0; i < smp_cpus; i++) {
o = OBJECT(&s->cpu[i]); Object *o = OBJECT(&s->cpu[i]);
/* On uniprocessor, the CBAR is set to 0 */ /* On uniprocessor, the CBAR is set to 0 */
if (smp_cpus > 1) { if (smp_cpus > 1) {
@ -205,16 +206,15 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
/* /*
* A7MPCORE * A7MPCORE
*/ */
object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", smp_cpus, object_property_set_int(OBJECT(mpcore), "num-cpu", smp_cpus, &error_abort);
&error_abort); object_property_set_int(OBJECT(mpcore), "num-irq",
object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
FSL_IMX7_MAX_IRQ + GIC_INTERNAL, &error_abort); FSL_IMX7_MAX_IRQ + GIC_INTERNAL, &error_abort);
sysbus_realize(SYS_BUS_DEVICE(mpcore), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort); gic = mpcore;
sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
for (i = 0; i < smp_cpus; i++) { for (i = 0; i < smp_cpus; i++) {
SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore); SysBusDevice *sbd = SYS_BUS_DEVICE(gic);
DeviceState *d = DEVICE(qemu_get_cpu(i)); DeviceState *d = DEVICE(qemu_get_cpu(i));
irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
@ -255,8 +255,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->gpt[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]); sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX7_GPTn_IRQ[i]));
FSL_IMX7_GPTn_IRQ[i]));
} }
/* /*
@ -298,12 +297,10 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
FSL_IMX7_GPIOn_ADDR[i]); FSL_IMX7_GPIOn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX7_GPIOn_LOW_IRQ[i]));
FSL_IMX7_GPIOn_LOW_IRQ[i]));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX7_GPIOn_HIGH_IRQ[i]));
FSL_IMX7_GPIOn_HIGH_IRQ[i]));
} }
/* /*
@ -355,8 +352,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
FSL_IMX7_SPIn_ADDR[i]); FSL_IMX7_SPIn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX7_SPIn_IRQ[i]));
FSL_IMX7_SPIn_IRQ[i]));
} }
/* /*
@ -381,8 +377,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]); sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX7_I2Cn_IRQ[i]));
FSL_IMX7_I2Cn_IRQ[i]));
} }
/* /*
@ -416,7 +411,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]); sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]);
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]); irq = qdev_get_gpio_in(gic, FSL_IMX7_UARTn_IRQ[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq);
} }
@ -454,9 +449,9 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]); sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]);
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0)); irq = qdev_get_gpio_in(gic, FSL_IMX7_ENET_IRQ(i, 0));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq); sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq);
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3)); irq = qdev_get_gpio_in(gic, FSL_IMX7_ENET_IRQ(i, 3));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq); sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq);
} }
@ -483,7 +478,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0, sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
FSL_IMX7_USDHCn_ADDR[i]); FSL_IMX7_USDHCn_ADDR[i]);
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]); irq = qdev_get_gpio_in(gic, FSL_IMX7_USDHCn_IRQ[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq); sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq);
} }
@ -522,8 +517,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]); sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
qdev_get_gpio_in(DEVICE(&s->a7mpcore), qdev_get_gpio_in(gic, FSL_IMX7_WDOGn_IRQ[i]));
FSL_IMX7_WDOGn_IRQ[i]));
} }
/* /*
@ -606,11 +600,11 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_MSI_IRQ); irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_MSI_IRQ);
qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq); qdev_connect_gpio_out(DEVICE(&s->pcie4_msi_irq), 0, irq);
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ); irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTA_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ); irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTB_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ); irq = qdev_get_gpio_in(gic, FSL_IMX7_PCI_INTC_IRQ);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0); irq = qdev_get_gpio_in(DEVICE(&s->pcie4_msi_irq), 0);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
@ -643,7 +637,7 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
FSL_IMX7_USBn_ADDR[i]); FSL_IMX7_USBn_ADDR[i]);
irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USBn_IRQ[i]); irq = qdev_get_gpio_in(gic, FSL_IMX7_USBn_IRQ[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq); sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq);
snprintf(name, NAME_SIZE, "usbmisc%d", i); snprintf(name, NAME_SIZE, "usbmisc%d", i);

2
hw/arm/virt.c
View File

@ -1746,7 +1746,7 @@ void virt_machine_done(Notifier *notifier, void *data)
vms->memmap[VIRT_PLATFORM_BUS].size, vms->memmap[VIRT_PLATFORM_BUS].size,
vms->irqmap[VIRT_PLATFORM_BUS]); vms->irqmap[VIRT_PLATFORM_BUS]);
} }
if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) < 0) {
exit(1); exit(1);
} }

21
hw/cpu/a15mpcore.c
View File

@ -164,17 +164,14 @@ static void a15mp_priv_class_init(ObjectClass *klass, void *data)
/* We currently have no saveable state */ /* We currently have no saveable state */
} }
static const TypeInfo a15mp_priv_info = { static const TypeInfo a15mp_types[] = {
.name = TYPE_A15MPCORE_PRIV, {
.parent = TYPE_SYS_BUS_DEVICE, .name = TYPE_A15MPCORE_PRIV,
.instance_size = sizeof(A15MPPrivState), .parent = TYPE_SYS_BUS_DEVICE,
.instance_init = a15mp_priv_initfn, .instance_size = sizeof(A15MPPrivState),
.class_init = a15mp_priv_class_init, .instance_init = a15mp_priv_initfn,
.class_init = a15mp_priv_class_init,
},
}; };
static void a15mp_register_types(void) DEFINE_TYPES(a15mp_types)
{
type_register_static(&a15mp_priv_info);
}
type_init(a15mp_register_types)

21
hw/cpu/a9mpcore.c
View File

@ -177,17 +177,14 @@ static void a9mp_priv_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, a9mp_priv_properties); device_class_set_props(dc, a9mp_priv_properties);
} }
static const TypeInfo a9mp_priv_info = { static const TypeInfo a9mp_types[] = {
.name = TYPE_A9MPCORE_PRIV, {
.parent = TYPE_SYS_BUS_DEVICE, .name = TYPE_A9MPCORE_PRIV,
.instance_size = sizeof(A9MPPrivState), .parent = TYPE_SYS_BUS_DEVICE,
.instance_init = a9mp_priv_initfn, .instance_size = sizeof(A9MPPrivState),
.class_init = a9mp_priv_class_init, .instance_init = a9mp_priv_initfn,
.class_init = a9mp_priv_class_init,
},
}; };
static void a9mp_register_types(void) DEFINE_TYPES(a9mp_types)
{
type_register_static(&a9mp_priv_info);
}
type_init(a9mp_register_types)

21
hw/cpu/arm11mpcore.c
View File

@ -152,17 +152,14 @@ static void mpcore_priv_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, mpcore_priv_properties); device_class_set_props(dc, mpcore_priv_properties);
} }
static const TypeInfo mpcore_priv_info = { static const TypeInfo arm11mp_types[] = {
.name = TYPE_ARM11MPCORE_PRIV, {
.parent = TYPE_SYS_BUS_DEVICE, .name = TYPE_ARM11MPCORE_PRIV,
.instance_size = sizeof(ARM11MPCorePriveState), .parent = TYPE_SYS_BUS_DEVICE,
.instance_init = mpcore_priv_initfn, .instance_size = sizeof(ARM11MPCorePriveState),
.class_init = mpcore_priv_class_init, .instance_init = mpcore_priv_initfn,
.class_init = mpcore_priv_class_init,
},
}; };
static void arm11mpcore_register_types(void) DEFINE_TYPES(arm11mp_types)
{
type_register_static(&mpcore_priv_info);
}
type_init(arm11mpcore_register_types)

29
hw/cpu/realview_mpcore.c
View File

@ -14,7 +14,6 @@
#include "hw/cpu/arm11mpcore.h" #include "hw/cpu/arm11mpcore.h"
#include "hw/intc/realview_gic.h" #include "hw/intc/realview_gic.h"
#include "hw/irq.h" #include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "qom/object.h" #include "qom/object.h"
#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore" #define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
@ -68,7 +67,6 @@ static void realview_mpcore_realize(DeviceState *dev, Error **errp)
int n; int n;
int i; int i;
qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->priv), errp)) { if (!sysbus_realize(SYS_BUS_DEVICE(&s->priv), errp)) {
return; return;
} }
@ -100,6 +98,7 @@ static void mpcore_rirq_init(Object *obj)
int i; int i;
object_initialize_child(obj, "a11priv", &s->priv, TYPE_ARM11MPCORE_PRIV); object_initialize_child(obj, "a11priv", &s->priv, TYPE_ARM11MPCORE_PRIV);
object_property_add_alias(obj, "num-cpu", OBJECT(&s->priv), "num-cpu");
privbusdev = SYS_BUS_DEVICE(&s->priv); privbusdev = SYS_BUS_DEVICE(&s->priv);
sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0)); sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0));
@ -108,29 +107,21 @@ static void mpcore_rirq_init(Object *obj)
} }
} }
static const Property mpcore_rirq_properties[] = {
DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
};
static void mpcore_rirq_class_init(ObjectClass *klass, void *data) static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
{ {
DeviceClass *dc = DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = realview_mpcore_realize; dc->realize = realview_mpcore_realize;
device_class_set_props(dc, mpcore_rirq_properties);
} }
static const TypeInfo mpcore_rirq_info = { static const TypeInfo realview_mpcore_types[] = {
.name = TYPE_REALVIEW_MPCORE_RIRQ, {
.parent = TYPE_SYS_BUS_DEVICE, .name = TYPE_REALVIEW_MPCORE_RIRQ,
.instance_size = sizeof(mpcore_rirq_state), .parent = TYPE_SYS_BUS_DEVICE,
.instance_init = mpcore_rirq_init, .instance_size = sizeof(mpcore_rirq_state),
.class_init = mpcore_rirq_class_init, .instance_init = mpcore_rirq_init,
.class_init = mpcore_rirq_class_init,
},
}; };
static void realview_mpcore_register_types(void) DEFINE_TYPES(realview_mpcore_types)
{
type_register_static(&mpcore_rirq_info);
}
type_init(realview_mpcore_register_types)

26
hw/net/cadence_gem.c
View File

@ -909,8 +909,8 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
/* Compare A, B, C */ /* Compare A, B, C */
for (j = 0; j < 3; j++) { for (j = 0; j < 3; j++) {
uint32_t cr0, cr1, mask, compare; uint32_t cr0, cr1, mask, compare, disable_mask;
uint16_t rx_cmp; uint32_t rx_cmp;
int offset; int offset;
int cr_idx = extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6, int cr_idx = extract32(reg, R_SCREENING_TYPE2_REG0_COMPARE_A_SHIFT + j * 6,
R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH); R_SCREENING_TYPE2_REG0_COMPARE_A_LENGTH);
@ -946,9 +946,25 @@ static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
break; break;
} }
rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset]; disable_mask =
mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE); FIELD_EX32(cr1, TYPE2_COMPARE_0_WORD_1, DISABLE_MASK);
compare = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE); if (disable_mask) {
/*
* If disable_mask is set, mask_value is used as an
* additional 2 byte Compare Value; that is equivalent
* to using the whole cr0 register as the comparison value.
* Load 32 bits of data from rx_buf, and set mask to
* all-ones so we compare all 32 bits.
*/
rx_cmp = ldl_le_p(rxbuf_ptr + offset);
mask = 0xFFFFFFFF;
compare = cr0;
} else {
rx_cmp = lduw_le_p(rxbuf_ptr + offset);
mask = FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, MASK_VALUE);
compare =
FIELD_EX32(cr0, TYPE2_COMPARE_0_WORD_0, COMPARE_VALUE);
}
if ((rx_cmp & mask) == (compare & mask)) { if ((rx_cmp & mask) == (compare & mask)) {
matched = true; matched = true;

4
include/hw/arm/boot.h
View File

@ -160,6 +160,7 @@ AddressSpace *arm_boot_address_space(ARMCPU *cpu,
* @binfo: struct describing the boot environment * @binfo: struct describing the boot environment
* @addr_limit: upper limit of the available memory area at @addr * @addr_limit: upper limit of the available memory area at @addr
* @as: address space to load image to * @as: address space to load image to
* @cpu: ARM CPU object
* *
* Load a device tree supplied by the machine or by the user with the * Load a device tree supplied by the machine or by the user with the
* '-dtb' command line option, and put it at offset @addr in target * '-dtb' command line option, and put it at offset @addr in target
@ -176,7 +177,8 @@ AddressSpace *arm_boot_address_space(ARMCPU *cpu,
* Note: Must not be called unless have_dtb(binfo) is true. * Note: Must not be called unless have_dtb(binfo) is true.
*/ */
int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
hwaddr addr_limit, AddressSpace *as, MachineState *ms); hwaddr addr_limit, AddressSpace *as, MachineState *ms,
ARMCPU *cpu);
/* Write a secure board setup routine with a dummy handler for SMCs */ /* Write a secure board setup routine with a dummy handler for SMCs */
void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,

4
linux-user/syscall.c
View File

@ -360,7 +360,8 @@ _syscall3(int, sys_sched_getaffinity, pid_t, pid, unsigned int, len,
#define __NR_sys_sched_setaffinity __NR_sched_setaffinity #define __NR_sys_sched_setaffinity __NR_sched_setaffinity
_syscall3(int, sys_sched_setaffinity, pid_t, pid, unsigned int, len, _syscall3(int, sys_sched_setaffinity, pid_t, pid, unsigned int, len,
unsigned long *, user_mask_ptr); unsigned long *, user_mask_ptr);
/* sched_attr is not defined in glibc */ /* sched_attr is not defined in glibc < 2.41 */
#ifndef SCHED_ATTR_SIZE_VER0
struct sched_attr { struct sched_attr {
uint32_t size; uint32_t size;
uint32_t sched_policy; uint32_t sched_policy;
@ -373,6 +374,7 @@ struct sched_attr {
uint32_t sched_util_min; uint32_t sched_util_min;
uint32_t sched_util_max; uint32_t sched_util_max;
}; };
#endif
#define __NR_sys_sched_getattr __NR_sched_getattr #define __NR_sys_sched_getattr __NR_sched_getattr
_syscall4(int, sys_sched_getattr, pid_t, pid, struct sched_attr *, attr, _syscall4(int, sys_sched_getattr, pid_t, pid, struct sched_attr *, attr,
unsigned int, size, unsigned int, flags); unsigned int, size, unsigned int, flags);

1
system/vl.c
View File

@ -3469,6 +3469,7 @@ void qemu_init(int argc, char **argv)
nb_prom_envs++; nb_prom_envs++;
break; break;
case QEMU_OPTION_old_param: case QEMU_OPTION_old_param:
warn_report("-old-param is deprecated");
old_param = 1; old_param = 1;
break; break;
case QEMU_OPTION_rtc: case QEMU_OPTION_rtc:

3
target/arm/cpu.c
View File

@ -2758,6 +2758,9 @@ static void cpu_register_class_init(ObjectClass *oc, void *data)
acc->info = data; acc->info = data;
cc->gdb_core_xml_file = "arm-core.xml"; cc->gdb_core_xml_file = "arm-core.xml";
if (acc->info->deprecation_note) {
cc->deprecation_note = acc->info->deprecation_note;
}
} }
void arm_cpu_register(const ARMCPUInfo *info) void arm_cpu_register(const ARMCPUInfo *info)

1
target/arm/cpu.h
View File

@ -1118,6 +1118,7 @@ struct ArchCPU {
typedef struct ARMCPUInfo { typedef struct ARMCPUInfo {
const char *name; const char *name;
const char *deprecation_note;
void (*initfn)(Object *obj); void (*initfn)(Object *obj);
void (*class_init)(ObjectClass *oc, void *data); void (*class_init)(ObjectClass *oc, void *data);
} ARMCPUInfo; } ARMCPUInfo;

36
target/arm/tcg/cpu32.c
View File

@ -1026,19 +1026,31 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
{ .name = "ti925t", .initfn = ti925t_initfn }, { .name = "ti925t", .initfn = ti925t_initfn },
{ .name = "sa1100", .initfn = sa1100_initfn }, { .name = "sa1100", .initfn = sa1100_initfn },
{ .name = "sa1110", .initfn = sa1110_initfn }, { .name = "sa1110", .initfn = sa1110_initfn },
{ .name = "pxa250", .initfn = pxa250_initfn }, { .name = "pxa250", .initfn = pxa250_initfn,
{ .name = "pxa255", .initfn = pxa255_initfn }, .deprecation_note = "iwMMXt CPUs are no longer supported", },
{ .name = "pxa260", .initfn = pxa260_initfn }, { .name = "pxa255", .initfn = pxa255_initfn,
{ .name = "pxa261", .initfn = pxa261_initfn }, .deprecation_note = "iwMMXt CPUs are no longer supported", },
{ .name = "pxa262", .initfn = pxa262_initfn }, { .name = "pxa260", .initfn = pxa260_initfn,
.deprecation_note = "iwMMXt CPUs are no longer supported", },
{ .name = "pxa261", .initfn = pxa261_initfn,
.deprecation_note = "iwMMXt CPUs are no longer supported", },
{ .name = "pxa262", .initfn = pxa262_initfn,
.deprecation_note = "iwMMXt CPUs are no longer supported", },
/* "pxa270" is an alias for "pxa270-a0" */ /* "pxa270" is an alias for "pxa270-a0" */
{ .name = "pxa270", .initfn = pxa270a0_initfn }, { .name = "pxa270", .initfn = pxa270a0_initfn,
{ .name = "pxa270-a0", .initfn = pxa270a0_initfn }, .deprecation_note = "iwMMXt CPUs are no longer supported", },
{ .name = "pxa270-a1", .initfn = pxa270a1_initfn }, { .name = "pxa270-a0", .initfn = pxa270a0_initfn,
{ .name = "pxa270-b0", .initfn = pxa270b0_initfn }, .deprecation_note = "iwMMXt CPUs are no longer supported", },
{ .name = "pxa270-b1", .initfn = pxa270b1_initfn }, { .name = "pxa270-a1", .initfn = pxa270a1_initfn,
{ .name = "pxa270-c0", .initfn = pxa270c0_initfn }, .deprecation_note = "iwMMXt CPUs are no longer supported", },
{ .name = "pxa270-c5", .initfn = pxa270c5_initfn }, { .name = "pxa270-b0", .initfn = pxa270b0_initfn,
.deprecation_note = "iwMMXt CPUs are no longer supported", },
{ .name = "pxa270-b1", .initfn = pxa270b1_initfn,
.deprecation_note = "iwMMXt CPUs are no longer supported", },
{ .name = "pxa270-c0", .initfn = pxa270c0_initfn,
.deprecation_note = "iwMMXt CPUs are no longer supported", },
{ .name = "pxa270-c5", .initfn = pxa270c5_initfn,
.deprecation_note = "iwMMXt CPUs are no longer supported", },
#ifndef TARGET_AARCH64 #ifndef TARGET_AARCH64
{ .name = "max", .initfn = arm_max_initfn }, { .name = "max", .initfn = arm_max_initfn },
#endif #endif

11
target/arm/tcg/translate-a64.c
View File

@ -75,17 +75,6 @@ static int scale_by_log2_tag_granule(DisasContext *s, int x)
#include "decode-sme-fa64.c.inc" #include "decode-sme-fa64.c.inc"
#include "decode-a64.c.inc" #include "decode-a64.c.inc"
/* Table based decoder typedefs - used when the relevant bits for decode
* are too awkwardly scattered across the instruction (eg SIMD).
*/
typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn);
typedef struct AArch64DecodeTable {
uint32_t pattern;
uint32_t mask;
AArch64DecodeFn *disas_fn;
} AArch64DecodeTable;
/* initialize TCG globals. */ /* initialize TCG globals. */
void a64_translate_init(void) void a64_translate_init(void)
{ {

7
tests/tcg/arm/Makefile.target
View File

@ -20,13 +20,6 @@ ARM_TESTS = hello-arm
hello-arm: CFLAGS+=-marm -ffreestanding -fno-stack-protector hello-arm: CFLAGS+=-marm -ffreestanding -fno-stack-protector
hello-arm: LDFLAGS+=-nostdlib hello-arm: LDFLAGS+=-nostdlib
# IWMXT floating point extensions
ARM_TESTS += test-arm-iwmmxt
# Clang assembler does not support IWMXT, so use the external assembler.
test-arm-iwmmxt: CFLAGS += -marm -march=iwmmxt -mabi=aapcs -mfpu=fpv4-sp-d16 $(CROSS_CC_HAS_FNIA)
test-arm-iwmmxt: test-arm-iwmmxt.S
$(CC) $(CFLAGS) -Wa,--noexecstack $< -o $@ $(LDFLAGS)
# Float-convert Tests # Float-convert Tests
ARM_TESTS += fcvt ARM_TESTS += fcvt
fcvt: LDFLAGS += -lm fcvt: LDFLAGS += -lm

5
tests/tcg/arm/README
View File

@ -4,8 +4,3 @@ hello-arm
--------- ---------
A very simple inline assembly, write syscall based hello world A very simple inline assembly, write syscall based hello world
test-arm-iwmmxt
---------------
A simple test case for older iwmmxt extended ARMs

49
tests/tcg/arm/test-arm-iwmmxt.S
View File

@ -1,49 +0,0 @@
@ Checks whether iwMMXt is functional.
.code 32
.globl main
main:
ldr r0, =data0
ldr r1, =data1
ldr r2, =data2
#ifndef FPA
wldrd wr0, [r0, #0]
wldrd wr1, [r0, #8]
wldrd wr2, [r1, #0]
wldrd wr3, [r1, #8]
wsubb wr2, wr2, wr0
wsubb wr3, wr3, wr1
wldrd wr0, [r2, #0]
wldrd wr1, [r2, #8]
waddb wr0, wr0, wr2
waddb wr1, wr1, wr3
wstrd wr0, [r2, #0]
wstrd wr1, [r2, #8]
#else
ldfe f0, [r0, #0]
ldfe f1, [r0, #8]
ldfe f2, [r1, #0]
ldfe f3, [r1, #8]
adfdp f2, f2, f0
adfdp f3, f3, f1
ldfe f0, [r2, #0]
ldfe f1, [r2, #8]
adfd f0, f0, f2
adfd f1, f1, f3
stfe f0, [r2, #0]
stfe f1, [r2, #8]
#endif
mov r0, #1
mov r1, r2
mov r2, #0x11
swi #0x900004
mov r0, #0
swi #0x900001
.data
data0:
.string "aaaabbbbccccdddd"
data1:
.string "bbbbccccddddeeee"
data2:
.string "hvLLWs\x1fsdrs9\x1fNJ-\n"