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target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward

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This optional behavior was removed from the ISA in v3.0, see
Summary of Changes preface:

  Data Storage Interrupt Status Register for Alignment Interrupt:
  Simplifies the Alignment interrupt by remov- ing the Data Storage
  Interrupt Status Register (DSISR) from the set of registers modified
  by the Alignment interrupt.

Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20230515092655.171206-5-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Nicholas Piggin 2023-05-15 19:26:50 +10:00 committed by Daniel Henrique Barboza
parent fbda88f7ab
commit 4ee5d2817f
1 changed files with 10 additions and 7 deletions
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17
target/ppc/excp_helper.c
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@ -1431,13 +1431,16 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
break; break;
} }
case POWERPC_EXCP_ALIGN: /* Alignment exception */ case POWERPC_EXCP_ALIGN: /* Alignment exception */
/* Get rS/rD and rA from faulting opcode */ /* Optional DSISR update was removed from ISA v3.0 */
/* if (!(env->insns_flags2 & PPC2_ISA300)) {
* Note: the opcode fields will not be set properly for a /* Get rS/rD and rA from faulting opcode */
* direct store load/store, but nobody cares as nobody /*
* actually uses direct store segments. * Note: the opcode fields will not be set properly for a
*/ * direct store load/store, but nobody cares as nobody
env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; * actually uses direct store segments.
*/
env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
}
break; break;
case POWERPC_EXCP_PROGRAM: /* Program exception */ case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) { switch (env->error_code & ~0xF) {