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target/arm: Convert CLS, CLZ (vector) to decodetree

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241211163036.2297116-39-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2024-12-11 10:30:05 -06:00 committed by Peter Maydell
parent 4fedfb483b
commit 4e728364c9
2 changed files with 19 additions and 20 deletions
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2
target/arm/tcg/a64.decode
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@ -1641,3 +1641,5 @@ SQABS_v 0.00 1110 ..1 00000 01111 0 ..... ..... @qrr_e
SQNEG_v 0.10 1110 ..1 00000 01111 0 ..... ..... @qrr_e SQNEG_v 0.10 1110 ..1 00000 01111 0 ..... ..... @qrr_e
ABS_v 0.00 1110 ..1 00000 10111 0 ..... ..... @qrr_e ABS_v 0.00 1110 ..1 00000 10111 0 ..... ..... @qrr_e
NEG_v 0.10 1110 ..1 00000 10111 0 ..... ..... @qrr_e NEG_v 0.10 1110 ..1 00000 10111 0 ..... ..... @qrr_e
CLS_v 0.00 1110 ..1 00000 01001 0 ..... ..... @qrr_e
CLZ_v 0.10 1110 ..1 00000 01001 0 ..... ..... @qrr_e

37
target/arm/tcg/translate-a64.c
View File

@ -8916,6 +8916,20 @@ static bool do_gvec_fn2(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
TRANS(ABS_v, do_gvec_fn2, a, tcg_gen_gvec_abs) TRANS(ABS_v, do_gvec_fn2, a, tcg_gen_gvec_abs)
TRANS(NEG_v, do_gvec_fn2, a, tcg_gen_gvec_neg) TRANS(NEG_v, do_gvec_fn2, a, tcg_gen_gvec_neg)
static bool do_gvec_fn2_bhs(DisasContext *s, arg_qrr_e *a, GVecGen2Fn *fn)
{
if (a->esz == MO_64) {
return false;
}
if (fp_access_check(s)) {
gen_gvec_fn2(s, a->q, a->rd, a->rn, fn, a->esz);
}
return true;
}
TRANS(CLS_v, do_gvec_fn2_bhs, a, gen_gvec_cls)
TRANS(CLZ_v, do_gvec_fn2_bhs, a, gen_gvec_clz)
/* Common vector code for handling integer to FP conversion */ /* Common vector code for handling integer to FP conversion */
static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
int elements, int is_signed, int elements, int is_signed,
@ -9215,13 +9229,6 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
TCGCond cond; TCGCond cond;
switch (opcode) { switch (opcode) {
case 0x4: /* CLS, CLZ */
if (u) {
tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64);
} else {
tcg_gen_clrsb_i64(tcg_rd, tcg_rn);
}
break;
case 0x5: /* NOT */ case 0x5: /* NOT */
/* This opcode is shared with CNT and RBIT but we have earlier /* This opcode is shared with CNT and RBIT but we have earlier
* enforced that size == 3 if and only if this is the NOT insn. * enforced that size == 3 if and only if this is the NOT insn.
@ -9283,6 +9290,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
gen_helper_frint64_d(tcg_rd, tcg_rn, tcg_fpstatus); gen_helper_frint64_d(tcg_rd, tcg_rn, tcg_fpstatus);
break; break;
default: default:
case 0x4: /* CLS, CLZ */
case 0x7: /* SQABS, SQNEG */ case 0x7: /* SQABS, SQNEG */
case 0xb: /* ABS, NEG */ case 0xb: /* ABS, NEG */
g_assert_not_reached(); g_assert_not_reached();
@ -10089,12 +10097,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd); handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd);
return; return;
case 0x4: /* CLS, CLZ */
if (size == 3) {
unallocated_encoding(s);
return;
}
break;
case 0x2: /* SADDLP, UADDLP */ case 0x2: /* SADDLP, UADDLP */
case 0x6: /* SADALP, UADALP */ case 0x6: /* SADALP, UADALP */
if (size == 3) { if (size == 3) {
@ -10299,6 +10301,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
} }
default: default:
case 0x3: /* SUQADD, USQADD */ case 0x3: /* SUQADD, USQADD */
case 0x4: /* CLS, CLZ */
case 0x7: /* SQABS, SQNEG */ case 0x7: /* SQABS, SQNEG */
case 0xb: /* ABS, NEG */ case 0xb: /* ABS, NEG */
unallocated_encoding(s); unallocated_encoding(s);
@ -10321,13 +10324,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
} }
switch (opcode) { switch (opcode) {
case 0x4: /* CLZ, CLS */
if (u) {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clz, size);
} else {
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_cls, size);
}
return;
case 0x5: case 0x5:
if (u && size == 0) { /* NOT */ if (u && size == 0) { /* NOT */
gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0); gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0);
@ -10351,6 +10347,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
case 0xa: /* CMLT */ case 0xa: /* CMLT */
gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size); gen_gvec_fn2(s, is_q, rd, rn, gen_gvec_clt0, size);
return; return;
case 0x4: /* CLZ, CLS */
case 0xb: case 0xb:
g_assert_not_reached(); g_assert_not_reached();
} }