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target/riscv: Update address modify functions to take into account pointer masking

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Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250106102346.1100149-6-baturo.alexey@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Alexey Baturo 2025-01-06 13:23:44 +03:00 committed by Alistair Francis
parent 6ec718e352
commit 4d501a7a7f
2 changed files with 32 additions and 6 deletions
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22
target/riscv/translate.c
View File

@ -589,8 +589,10 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
tcg_gen_addi_tl(addr, src1, imm); tcg_gen_addi_tl(addr, src1, imm);
if (get_address_xl(ctx) == MXL_RV32) { if (ctx->addr_signed) {
tcg_gen_ext32u_tl(addr, addr); tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_xl);
} else {
tcg_gen_extract_tl(addr, addr, 0, ctx->addr_xl);
} }
return addr; return addr;
@ -603,8 +605,10 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
tcg_gen_add_tl(addr, src1, offs); tcg_gen_add_tl(addr, src1, offs);
if (get_xl(ctx) == MXL_RV32) { if (ctx->addr_signed) {
tcg_gen_ext32u_tl(addr, addr); tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_xl);
} else {
tcg_gen_extract_tl(addr, addr, 0, ctx->addr_xl);
} }
return addr; return addr;
@ -1234,8 +1238,14 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
ctx->cs = cs; ctx->cs = cs;
ctx->addr_xl = 0; if (get_xl(ctx) == MXL_RV32) {
ctx->addr_signed = false; ctx->addr_xl = 32;
ctx->addr_signed = false;
} else {
int pm_pmm = FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM);
ctx->addr_xl = 64 - riscv_pm_get_pmlen(pm_pmm);
ctx->addr_signed = FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND);
}
ctx->ztso = cpu->cfg.ext_ztso; ctx->ztso = cpu->cfg.ext_ztso;
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
ctx->bcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED); ctx->bcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED);

16
target/riscv/vector_helper.c
View File

@ -107,6 +107,22 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr) static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
{ {
if (riscv_cpu_mxl(env) == MXL_RV32) {
return addr;
}
RISCVPmPmm pmm = riscv_pm_get_pmm(env);
if (pmm == PMM_FIELD_DISABLED) {
return addr;
}
int pmlen = riscv_pm_get_pmlen(pmm);
bool signext = riscv_cpu_virt_mem_enabled(env);
addr = addr << pmlen;
/* sign/zero extend masked address by N-1 bit */
if (signext) {
addr = (target_long)addr >> pmlen;
} else {
addr = addr >> pmlen;
}
return addr; return addr;
} }