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target/ppc: Add SMT support to PTCR SPR

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PTCR is a per-core register.

Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2023-07-12 23:02:00 +10:00
parent e5c2ac9dc1
commit 4d2b0ad32a
2 changed files with 18 additions and 2 deletions
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16
target/ppc/misc_helper.c
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@ -173,6 +173,7 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val)
void helper_store_ptcr(CPUPPCState *env, target_ulong val) void helper_store_ptcr(CPUPPCState *env, target_ulong val)
{ {
if (env->spr[SPR_PTCR] != val) { if (env->spr[SPR_PTCR] != val) {
CPUState *cs = env_cpu(env);
PowerPCCPU *cpu = env_archcpu(env); PowerPCCPU *cpu = env_archcpu(env);
target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS; target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS;
target_ulong patbsize = val & PTCR_PATS; target_ulong patbsize = val & PTCR_PATS;
@ -194,8 +195,19 @@ void helper_store_ptcr(CPUPPCState *env, target_ulong val)
return; return;
} }
env->spr[SPR_PTCR] = val; if (cs->nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
tlb_flush(env_cpu(env)); env->spr[SPR_PTCR] = val;
tlb_flush(cs);
} else {
CPUState *ccs;
THREAD_SIBLING_FOREACH(cs, ccs) {
PowerPCCPU *ccpu = POWERPC_CPU(ccs);
CPUPPCState *cenv = &ccpu->env;
cenv->spr[SPR_PTCR] = val;
tlb_flush(ccs);
}
}
} }
} }

4
target/ppc/translate.c
View File

@ -909,6 +909,10 @@ void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
} }
void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
{ {
if (!gen_serialize_core(ctx)) {
return;
}
gen_helper_store_ptcr(tcg_env, cpu_gpr[gprn]); gen_helper_store_ptcr(tcg_env, cpu_gpr[gprn]);
} }