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target/ppc: add support for Hypervisor Facility Unavailable Exception

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The privileged message send and clear instructions (msgsndp & msgclrp)
are privileged, but will generate a hypervisor facility unavailable
exception if not enabled in the HFSCR and executed in privileged
non-hypervisor state.

Add checks when accessing the DPDES register and when using the
msgsndp and msgclrp isntructions.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20200120104935.24449-3-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater 2020-01-20 11:49:35 +01:00 committed by David Gibson
parent 5ba7ba1da0
commit 493028d8d7
3 changed files with 46 additions and 0 deletions
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6
target/ppc/cpu.h
View File

@ -397,6 +397,10 @@ typedef struct ppc_v3_pate_t {
#define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */ #define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */
#define PSSCR_EC PPC_BIT(43) /* Exit Criterion */ #define PSSCR_EC PPC_BIT(43) /* Exit Criterion */
/* HFSCR bits */
#define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */
#define HFSCR_IC_MSGP 0xA
#define msr_sf ((env->msr >> MSR_SF) & 1) #define msr_sf ((env->msr >> MSR_SF) & 1)
#define msr_isf ((env->msr >> MSR_ISF) & 1) #define msr_isf ((env->msr >> MSR_ISF) & 1)
#define msr_shv ((env->msr >> MSR_SHV) & 1) #define msr_shv ((env->msr >> MSR_SHV) & 1)
@ -1329,6 +1333,8 @@ void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
#endif #endif
void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask); void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
const char *caller, uint32_t cause);
static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn) static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
{ {

13
target/ppc/excp_helper.c
View File

@ -471,6 +471,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
case POWERPC_EXCP_FU: /* Facility unavailable exception */ case POWERPC_EXCP_FU: /* Facility unavailable exception */
#ifdef TARGET_PPC64 #ifdef TARGET_PPC64
env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56); env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
#endif
break;
case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
#ifdef TARGET_PPC64
env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
srr0 = SPR_HSRR0;
srr1 = SPR_HSRR1;
new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
#endif #endif
break; break;
case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */ case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
@ -1277,6 +1286,8 @@ void helper_book3s_msgsnd(target_ulong rb)
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb) void helper_book3s_msgclrp(CPUPPCState *env, target_ulong rb)
{ {
helper_hfscr_facility_check(env, HFSCR_MSGP, "msgclrp", HFSCR_IC_MSGP);
if (!dbell_type_server(rb)) { if (!dbell_type_server(rb)) {
return; return;
} }
@ -1292,6 +1303,8 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb)
{ {
int pir = env->spr_cb[SPR_PIR].default_value; int pir = env->spr_cb[SPR_PIR].default_value;
helper_hfscr_facility_check(env, HFSCR_MSGP, "msgsndp", HFSCR_IC_MSGP);
if (!dbell_type_server(rb)) { if (!dbell_type_server(rb)) {
return; return;
} }

27
target/ppc/misc_helper.c
View File

@ -41,6 +41,18 @@ void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
} }
#ifdef TARGET_PPC64 #ifdef TARGET_PPC64
static void raise_hv_fu_exception(CPUPPCState *env, uint32_t bit,
const char *caller, uint32_t cause,
uintptr_t raddr)
{
qemu_log_mask(CPU_LOG_INT, "HV Facility %d is unavailable (%s)\n",
bit, caller);
env->spr[SPR_HFSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
raise_exception_err_ra(env, POWERPC_EXCP_HV_FU, cause, raddr);
}
static void raise_fu_exception(CPUPPCState *env, uint32_t bit, static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
uint32_t sprn, uint32_t cause, uint32_t sprn, uint32_t cause,
uintptr_t raddr) uintptr_t raddr)
@ -55,6 +67,17 @@ static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
} }
#endif #endif
void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
const char *caller, uint32_t cause)
{
#ifdef TARGET_PPC64
if ((env->msr_mask & MSR_HVB) && !msr_hv &&
!(env->spr[SPR_HFSCR] & (1UL << bit))) {
raise_hv_fu_exception(env, bit, caller, cause, GETPC());
}
#endif
}
void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit, void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
uint32_t sprn, uint32_t cause) uint32_t sprn, uint32_t cause)
{ {
@ -114,6 +137,8 @@ target_ulong helper_load_dpdes(CPUPPCState *env)
{ {
target_ulong dpdes = 0; target_ulong dpdes = 0;
helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MSGP);
/* TODO: TCG supports only one thread */ /* TODO: TCG supports only one thread */
if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) {
dpdes = 1; dpdes = 1;
@ -127,6 +152,8 @@ void helper_store_dpdes(CPUPPCState *env, target_ulong val)
PowerPCCPU *cpu = env_archcpu(env); PowerPCCPU *cpu = env_archcpu(env);
CPUState *cs = CPU(cpu); CPUState *cs = CPU(cpu);
helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_MSGP);
/* TODO: TCG supports only one thread */ /* TODO: TCG supports only one thread */
if (val & ~0x1) { if (val & ~0x1) {
qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value " qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value "