target/ppc: Fix misindented qemu_log_mask() calls

Fix several qemu_log_mask() calls that are misindented.

Acked-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
BALATON Zoltan 2024-05-13 01:27:47 +02:00 committed by Nicholas Piggin
parent 77d9607d71
commit 47bededc29

View File

@ -315,8 +315,8 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
int ret = -1; int ret = -1;
bool ifetch = access_type == MMU_INST_FETCH; bool ifetch = access_type == MMU_INST_FETCH;
qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT v " TARGET_FMT_lx "\n", __func__, qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT v " TARGET_FMT_lx "\n", __func__,
ifetch ? 'I' : 'D', virtual); ifetch ? 'I' : 'D', virtual);
if (ifetch) { if (ifetch) {
BATlt = env->IBAT[1]; BATlt = env->IBAT[1];
BATut = env->IBAT[0]; BATut = env->IBAT[0];
@ -330,9 +330,9 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
BEPIu = *BATu & 0xF0000000; BEPIu = *BATu & 0xF0000000;
BEPIl = *BATu & 0x0FFE0000; BEPIl = *BATu & 0x0FFE0000;
bat_size_prot(env, &bl, &valid, &prot, BATu, BATl); bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v " TARGET_FMT_lx " BATu " qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v " TARGET_FMT_lx " BATu "
TARGET_FMT_lx " BATl " TARGET_FMT_lx "\n", __func__, TARGET_FMT_lx " BATl " TARGET_FMT_lx "\n", __func__,
ifetch ? 'I' : 'D', i, virtual, *BATu, *BATl); ifetch ? 'I' : 'D', i, virtual, *BATu, *BATl);
if ((virtual & 0xF0000000) == BEPIu && if ((virtual & 0xF0000000) == BEPIu &&
((virtual & 0x0FFE0000) & ~bl) == BEPIl) { ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
/* BAT matches */ /* BAT matches */
@ -364,12 +364,11 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
BEPIu = *BATu & 0xF0000000; BEPIu = *BATu & 0xF0000000;
BEPIl = *BATu & 0x0FFE0000; BEPIl = *BATu & 0x0FFE0000;
bl = (*BATu & 0x00001FFC) << 15; bl = (*BATu & 0x00001FFC) << 15;
qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v " qemu_log_mask(CPU_LOG_MMU, "%s: %cBAT%d v " TARGET_FMT_lx
TARGET_FMT_lx " BATu " TARGET_FMT_lx " BATu " TARGET_FMT_lx " BATl " TARGET_FMT_lx
" BATl " TARGET_FMT_lx "\n\t" TARGET_FMT_lx " " "\n\t" TARGET_FMT_lx " " TARGET_FMT_lx " "
TARGET_FMT_lx " " TARGET_FMT_lx "\n", TARGET_FMT_lx "\n", __func__, ifetch ? 'I' : 'D',
__func__, ifetch ? 'I' : 'D', i, virtual, i, virtual, *BATu, *BATl, BEPIu, BEPIl, bl);
*BATu, *BATl, BEPIu, BEPIl, bl);
} }
} }
} }
@ -415,9 +414,8 @@ static int mmu6xx_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
hash = vsid ^ pgidx; hash = vsid ^ pgidx;
ctx->ptem = (vsid << 7) | (pgidx >> 10); ctx->ptem = (vsid << 7) | (pgidx >> 10);
qemu_log_mask(CPU_LOG_MMU, qemu_log_mask(CPU_LOG_MMU, "pte segment: key=%d ds %d nx %d vsid "
"pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n", TARGET_FMT_lx "\n", ctx->key, ds, ctx->nx, vsid);
ctx->key, ds, ctx->nx, vsid);
if (!ds) { if (!ds) {
/* Check if instruction fetch is allowed, if needed */ /* Check if instruction fetch is allowed, if needed */
if (type == ACCESS_CODE && ctx->nx) { if (type == ACCESS_CODE && ctx->nx) {
@ -583,9 +581,9 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
return 0; return 0;
} }
} }
qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx
" => " HWADDR_FMT_plx " => " HWADDR_FMT_plx " %d %d\n",
" %d %d\n", __func__, address, raddr, ctx->prot, ret); __func__, address, raddr, ctx->prot, ret);
return ret; return ret;
} }
@ -704,11 +702,11 @@ int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, hwaddr *raddrp,
} }
mask = ~(booke206_tlb_to_page_size(env, tlb) - 1); mask = ~(booke206_tlb_to_page_size(env, tlb) - 1);
qemu_log_mask(CPU_LOG_MMU, "%s: TLB ADDR=0x" TARGET_FMT_lx qemu_log_mask(CPU_LOG_MMU, "%s: TLB ADDR=0x" TARGET_FMT_lx
" PID=0x%x MAS1=0x%x MAS2=0x%" PRIx64 " mask=0x%" " PID=0x%x MAS1=0x%x MAS2=0x%" PRIx64 " mask=0x%"
HWADDR_PRIx " MAS7_3=0x%" PRIx64 " MAS8=0x%" PRIx32 "\n", HWADDR_PRIx " MAS7_3=0x%" PRIx64 " MAS8=0x%" PRIx32 "\n",
__func__, address, pid, tlb->mas1, tlb->mas2, mask, __func__, address, pid, tlb->mas1, tlb->mas2, mask,
tlb->mas7_3, tlb->mas8); tlb->mas7_3, tlb->mas8);
/* Check PID */ /* Check PID */
tlb_pid = (tlb->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT; tlb_pid = (tlb->mas1 & MAS1_TID_MASK) >> MAS1_TID_SHIFT;