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target/hppa: Fix assemble_12a insns for wide mode

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Tested-by: Helge Deller <deller@gmx.de>
Reported-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-03-02 15:48:48 -10:00
parent 4768c28edd
commit 46174e140d
2 changed files with 33 additions and 11 deletions
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27
target/hppa/insns.decode
View File

@ -26,7 +26,7 @@
%assemble_11a 4:12 0:1 !function=expand_11a %assemble_11a 4:12 0:1 !function=expand_11a
%assemble_12 0:s1 2:1 3:10 !function=expand_shl2 %assemble_12 0:s1 2:1 3:10 !function=expand_shl2
%assemble_12a 0:s1 3:11 !function=expand_shl2 %assemble_12a 3:13 0:1 !function=expand_12a
%assemble_16 0:16 !function=expand_16 %assemble_16 0:16 !function=expand_16
%assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2 %assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2
%assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2 %assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2
@ -314,8 +314,9 @@ fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi
@ldstim14m ...... b:5 t:5 ................ \ @ldstim14m ...... b:5 t:5 ................ \
&ldst sp=%assemble_sp disp=%assemble_16 \ &ldst sp=%assemble_sp disp=%assemble_16 \
x=0 scale=0 m=%neg_to_m x=0 scale=0 m=%neg_to_m
@ldstim12m ...... b:5 t:5 sp:2 .............. \ @ldstim12m ...... b:5 t:5 ................ \
&ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m &ldst sp=%assemble_sp disp=%assemble_12a \
x=0 scale=0 m=%pos_to_m
# LDB, LDH, LDW, LDWM # LDB, LDH, LDW, LDWM
ld 010000 ..... ..... .. .............. @ldstim14 size=0 ld 010000 ..... ..... .. .............. @ldstim14 size=0
@ -331,15 +332,19 @@ st 011010 ..... ..... .. .............. @ldstim14 size=2
st 011011 ..... ..... .. .............. @ldstim14m size=2 st 011011 ..... ..... .. .............. @ldstim14m size=2
st 011111 ..... ..... .. ...........10. @ldstim12m size=2 st 011111 ..... ..... .. ...........10. @ldstim12m size=2
fldw 010110 b:5 ..... sp:2 .............. \ fldw 010110 b:5 ..... ................ \
&ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 &ldst disp=%assemble_12a sp=%assemble_sp \
fldw 010111 b:5 ..... sp:2 ...........0.. \ t=%rm64 m=%a_to_m x=0 scale=0 size=2
&ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 fldw 010111 b:5 ..... .............0.. \
&ldst disp=%assemble_12a sp=%assemble_sp \
t=%rm64 m=0 x=0 scale=0 size=2
fstw 011110 b:5 ..... sp:2 .............. \ fstw 011110 b:5 ..... ................ \
&ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 &ldst disp=%assemble_12a sp=%assemble_sp \
fstw 011111 b:5 ..... sp:2 ...........0.. \ t=%rm64 m=%a_to_m x=0 scale=0 size=2
&ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 fstw 011111 b:5 ..... .............0.. \
&ldst disp=%assemble_12a sp=%assemble_sp \
t=%rm64 m=0 x=0 scale=0 size=2
ld 010100 ..... ..... .. ............0. @ldstim11 ld 010100 ..... ..... .. ............0. @ldstim11
fldd 010100 ..... ..... .. ............1. @ldstim11 fldd 010100 ..... ..... .. ............1. @ldstim11

17
target/hppa/translate.c
View File

@ -155,6 +155,23 @@ static int expand_11a(DisasContext *ctx, int val)
return i; return i;
} }
/* Expander for assemble_16a(s,im11a,i). */
static int expand_12a(DisasContext *ctx, int val)
{
/*
* @val is bit 0 and bits [3:15].
* Swizzle thing around depending on PSW.W.
*/
int im11a = extract32(val, 1, 11);
int s = extract32(val, 12, 2);
int i = (-(val & 1) << 13) | (im11a << 2);
if (ctx->tb_flags & PSW_W) {
i ^= s << 13;
}
return i;
}
/* Expander for assemble_16(s,im14). */ /* Expander for assemble_16(s,im14). */
static int expand_16(DisasContext *ctx, int val) static int expand_16(DisasContext *ctx, int val)
{ {