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target/riscv/debug.c: use wp size = 4 for 32-bit CPUs

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The mcontrol select bit (19) is always zero, meaning our triggers will
always match virtual addresses. In this condition, if the user does not
specify a size for the trigger, the access size defaults to XLEN.

At this moment we're using def_size = 8 regardless of CPU XLEN. Use
def_size = 4 in case we're running 32 bits.

Fixes: 95799e36c1 ("target/riscv: Add initial support for the Sdtrig extension")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250121170626.1992570-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Daniel Henrique Barboza 2025-01-21 14:06:25 -03:00 committed by Alistair Francis
parent bf3adf93f1
commit 3fba76e61c
1 changed files with 4 additions and 2 deletions
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6
target/riscv/debug.c
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@ -478,7 +478,7 @@ static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index)
bool enabled = type2_breakpoint_enabled(ctrl); bool enabled = type2_breakpoint_enabled(ctrl);
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
int flags = BP_CPU | BP_STOP_BEFORE_ACCESS; int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
uint32_t size; uint32_t size, def_size;
if (!enabled) { if (!enabled) {
return; return;
@ -501,7 +501,9 @@ static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index)
cpu_watchpoint_insert(cs, addr, size, flags, cpu_watchpoint_insert(cs, addr, size, flags,
&env->cpu_watchpoint[index]); &env->cpu_watchpoint[index]);
} else { } else {
cpu_watchpoint_insert(cs, addr, 8, flags, def_size = riscv_cpu_mxl(env) == MXL_RV64 ? 8 : 4;
cpu_watchpoint_insert(cs, addr, def_size, flags,
&env->cpu_watchpoint[index]); &env->cpu_watchpoint[index]);
} }
} }