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target/arm: Tidy handle_vec_simd_shri

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Now that we've converted all cases to gvec, there is quite a bit
of dead code at the end of the function.  Remove it.

Sink the call to gen_gvec_fn2i to the end, loading a function
pointer within the switch statement.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200513163245.17915-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-05-13 09:32:34 -07:00 committed by Peter Maydell
parent 2f27c5244d
commit 3f08f0bce8
1 changed files with 14 additions and 42 deletions
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56
target/arm/translate-a64.c
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@ -10155,16 +10155,7 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
int size = 32 - clz32(immh) - 1; int size = 32 - clz32(immh) - 1;
int immhb = immh << 3 | immb; int immhb = immh << 3 | immb;
int shift = 2 * (8 << size) - immhb; int shift = 2 * (8 << size) - immhb;
bool accumulate = false; GVecGen2iFn *gvec_fn;
int dsize = is_q ? 128 : 64;
int esize = 8 << size;
int elements = dsize/esize;
MemOp memop = size | (is_u ? 0 : MO_SIGN);
TCGv_i64 tcg_rn = new_tmp_a64(s);
TCGv_i64 tcg_rd = new_tmp_a64(s);
TCGv_i64 tcg_round;
uint64_t round_const;
int i;
if (extract32(immh, 3, 1) && !is_q) { if (extract32(immh, 3, 1) && !is_q) {
unallocated_encoding(s); unallocated_encoding(s);
@ -10178,13 +10169,12 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
switch (opcode) { switch (opcode) {
case 0x02: /* SSRA / USRA (accumulate) */ case 0x02: /* SSRA / USRA (accumulate) */
gen_gvec_fn2i(s, is_q, rd, rn, shift, gvec_fn = is_u ? gen_gvec_usra : gen_gvec_ssra;
is_u ? gen_gvec_usra : gen_gvec_ssra, size); break;
return;
case 0x08: /* SRI */ case 0x08: /* SRI */
gen_gvec_fn2i(s, is_q, rd, rn, shift, gen_gvec_sri, size); gvec_fn = gen_gvec_sri;
return; break;
case 0x00: /* SSHR / USHR */ case 0x00: /* SSHR / USHR */
if (is_u) { if (is_u) {
@ -10192,49 +10182,31 @@ static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
/* Shift count the same size as element size produces zero. */ /* Shift count the same size as element size produces zero. */
tcg_gen_gvec_dup_imm(size, vec_full_reg_offset(s, rd), tcg_gen_gvec_dup_imm(size, vec_full_reg_offset(s, rd),
is_q ? 16 : 8, vec_full_reg_size(s), 0); is_q ? 16 : 8, vec_full_reg_size(s), 0);
} else { return;
gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shri, size);
} }
gvec_fn = tcg_gen_gvec_shri;
} else { } else {
/* Shift count the same size as element size produces all sign. */ /* Shift count the same size as element size produces all sign. */
if (shift == 8 << size) { if (shift == 8 << size) {
shift -= 1; shift -= 1;
} }
gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_sari, size); gvec_fn = tcg_gen_gvec_sari;
} }
return; break;
case 0x04: /* SRSHR / URSHR (rounding) */ case 0x04: /* SRSHR / URSHR (rounding) */
gen_gvec_fn2i(s, is_q, rd, rn, shift, gvec_fn = is_u ? gen_gvec_urshr : gen_gvec_srshr;
is_u ? gen_gvec_urshr : gen_gvec_srshr, size); break;
return;
case 0x06: /* SRSRA / URSRA (accum + rounding) */ case 0x06: /* SRSRA / URSRA (accum + rounding) */
gen_gvec_fn2i(s, is_q, rd, rn, shift, gvec_fn = is_u ? gen_gvec_ursra : gen_gvec_srsra;
is_u ? gen_gvec_ursra : gen_gvec_srsra, size); break;
return;
default: default:
g_assert_not_reached(); g_assert_not_reached();
} }
round_const = 1ULL << (shift - 1); gen_gvec_fn2i(s, is_q, rd, rn, shift, gvec_fn, size);
tcg_round = tcg_const_i64(round_const);
for (i = 0; i < elements; i++) {
read_vec_element(s, tcg_rn, rn, i, memop);
if (accumulate) {
read_vec_element(s, tcg_rd, rd, i, memop);
}
handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
accumulate, is_u, size, shift);
write_vec_element(s, tcg_rd, rd, i, size);
}
tcg_temp_free_i64(tcg_round);
clear_vec_high(s, is_q, rd);
} }
/* SHL/SLI - Vector shift left */ /* SHL/SLI - Vector shift left */