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target/mips: Add MO_ALIGN to gen_llwp, gen_scwp

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These are atomic operations, so mark as requiring alignment.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-05-02 10:01:56 +01:00
parent 9490142284
commit 3ec02c1f0f
1 changed files with 3 additions and 2 deletions
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5
target/mips/tcg/nanomips_translate.c.inc
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@ -998,7 +998,7 @@ static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
TCGv tmp2 = tcg_temp_new(); TCGv tmp2 = tcg_temp_new();
gen_base_offset_addr(ctx, taddr, base, offset); gen_base_offset_addr(ctx, taddr, base, offset);
tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ); tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx, MO_TEUQ | MO_ALIGN);
if (cpu_is_bigendian(ctx)) { if (cpu_is_bigendian(ctx)) {
tcg_gen_extr_i64_tl(tmp2, tmp1, tval); tcg_gen_extr_i64_tl(tmp2, tmp1, tval);
} else { } else {
@ -1039,7 +1039,8 @@ static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp)); tcg_gen_ld_i64(llval, cpu_env, offsetof(CPUMIPSState, llval_wp));
tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval, tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,
eva ? MIPS_HFLAG_UM : ctx->mem_idx, MO_64); eva ? MIPS_HFLAG_UM : ctx->mem_idx,
MO_64 | MO_ALIGN);
if (reg1 != 0) { if (reg1 != 0) {
tcg_gen_movi_tl(cpu_gpr[reg1], 1); tcg_gen_movi_tl(cpu_gpr[reg1], 1);
} }