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target/i386: Avoid use of tcg_const_* throughout

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All uses are strictly read-only.  Most of the obviously so,
as direct arguments to gen_helper_*.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-02-25 13:26:02 -10:00
parent 0992a93013
commit 3df11bb14a
1 changed files with 42 additions and 41 deletions
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83
target/i386/tcg/translate.c
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@ -884,7 +884,7 @@ static void gen_compute_eflags(DisasContext *s)
live = cc_op_live[s->cc_op] & ~USES_CC_SRCT; live = cc_op_live[s->cc_op] & ~USES_CC_SRCT;
dead = live ^ (USES_CC_DST | USES_CC_SRC | USES_CC_SRC2); dead = live ^ (USES_CC_DST | USES_CC_SRC | USES_CC_SRC2);
if (dead) { if (dead) {
zero = tcg_const_tl(0); zero = tcg_constant_tl(0);
if (dead & USES_CC_DST) { if (dead & USES_CC_DST) {
dst = zero; dst = zero;
} }
@ -1412,7 +1412,7 @@ static void gen_helper_fp_arith_ST0_FT0(int op)
/* NOTE the exception in "r" op ordering */ /* NOTE the exception in "r" op ordering */
static void gen_helper_fp_arith_STN_ST0(int op, int opreg) static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
{ {
TCGv_i32 tmp = tcg_const_i32(opreg); TCGv_i32 tmp = tcg_constant_i32(opreg);
switch (op) { switch (op) {
case 0: case 0:
gen_helper_fadd_STN_ST0(cpu_env, tmp); gen_helper_fadd_STN_ST0(cpu_env, tmp);
@ -1439,7 +1439,7 @@ static void gen_exception(DisasContext *s, int trapno)
{ {
gen_update_cc_op(s); gen_update_cc_op(s);
gen_update_eip_cur(s); gen_update_eip_cur(s);
gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); gen_helper_raise_exception(cpu_env, tcg_constant_i32(trapno));
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
} }
@ -1633,7 +1633,7 @@ static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result,
/* Store the results into the CC variables. If we know that the /* Store the results into the CC variables. If we know that the
variable must be dead, store unconditionally. Otherwise we'll variable must be dead, store unconditionally. Otherwise we'll
need to not disrupt the current contents. */ need to not disrupt the current contents. */
z_tl = tcg_const_tl(0); z_tl = tcg_constant_tl(0);
if (cc_op_live[s->cc_op] & USES_CC_DST) { if (cc_op_live[s->cc_op] & USES_CC_DST) {
tcg_gen_movcond_tl(TCG_COND_NE, cpu_cc_dst, count, z_tl, tcg_gen_movcond_tl(TCG_COND_NE, cpu_cc_dst, count, z_tl,
result, cpu_cc_dst); result, cpu_cc_dst);
@ -1657,7 +1657,7 @@ static void gen_shift_flags(DisasContext *s, MemOp ot, TCGv result,
} }
/* Conditionally store the CC_OP value. */ /* Conditionally store the CC_OP value. */
z32 = tcg_const_i32(0); z32 = tcg_constant_i32(0);
s32 = tcg_temp_new_i32(); s32 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(s32, count); tcg_gen_trunc_tl_i32(s32, count);
tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, s32, z32, s->tmp2_i32, oldop); tcg_gen_movcond_i32(TCG_COND_NE, cpu_cc_op, s32, z32, s->tmp2_i32, oldop);
@ -1813,7 +1813,7 @@ static void gen_rot_rm_T1(DisasContext *s, MemOp ot, int op1, int is_right)
is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live. is 0 we keep the CC_OP_EFLAGS setting so that only CC_SRC is live.
Otherwise reuse CC_OP_ADCOX which have the C and O flags split out Otherwise reuse CC_OP_ADCOX which have the C and O flags split out
exactly as we computed above. */ exactly as we computed above. */
t0 = tcg_const_i32(0); t0 = tcg_constant_i32(0);
t1 = tcg_temp_new_i32(); t1 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t1, s->T1); tcg_gen_trunc_tl_i32(t1, s->T1);
tcg_gen_movi_i32(s->tmp2_i32, CC_OP_ADCOX); tcg_gen_movi_i32(s->tmp2_i32, CC_OP_ADCOX);
@ -2497,7 +2497,7 @@ static void gen_cmovcc1(CPUX86State *env, DisasContext *s, MemOp ot, int b,
cc.reg = t0; cc.reg = t0;
} }
if (!cc.use_reg2) { if (!cc.use_reg2) {
cc.reg2 = tcg_const_tl(cc.imm); cc.reg2 = tcg_constant_tl(cc.imm);
} }
tcg_gen_movcond_tl(cc.cond, s->T0, cc.reg, cc.reg2, tcg_gen_movcond_tl(cc.cond, s->T0, cc.reg, cc.reg2,
@ -2525,7 +2525,7 @@ static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg)
{ {
if (PE(s) && !VM86(s)) { if (PE(s) && !VM86(s)) {
tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0);
gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), s->tmp2_i32); gen_helper_load_seg(cpu_env, tcg_constant_i32(seg_reg), s->tmp2_i32);
/* abort translation because the addseg value may change or /* abort translation because the addseg value may change or
because ss32 may change. For R_SS, translation must always because ss32 may change. For R_SS, translation must always
stop as a special handling must be done to disable hardware stop as a special handling must be done to disable hardware
@ -4344,7 +4344,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
gen_op_mov_v_reg(s, ot, s->T1, reg); gen_op_mov_v_reg(s, ot, s->T1, reg);
if (shift) { if (shift) {
TCGv imm = tcg_const_tl(x86_ldub_code(env, s)); TCGv imm = tcg_constant_tl(x86_ldub_code(env, s));
gen_shiftd_rm_T1(s, ot, opreg, op, imm); gen_shiftd_rm_T1(s, ot, opreg, op, imm);
} else { } else {
gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]); gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]);
@ -4503,7 +4503,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
break; break;
case 0x0c: /* fldenv mem */ case 0x0c: /* fldenv mem */
gen_helper_fldenv(cpu_env, s->A0, gen_helper_fldenv(cpu_env, s->A0,
tcg_const_i32(dflag - 1)); tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false; update_fip = update_fdp = false;
break; break;
case 0x0d: /* fldcw mem */ case 0x0d: /* fldcw mem */
@ -4514,7 +4514,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
break; break;
case 0x0e: /* fnstenv mem */ case 0x0e: /* fnstenv mem */
gen_helper_fstenv(cpu_env, s->A0, gen_helper_fstenv(cpu_env, s->A0,
tcg_const_i32(dflag - 1)); tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false; update_fip = update_fdp = false;
break; break;
case 0x0f: /* fnstcw mem */ case 0x0f: /* fnstcw mem */
@ -4532,12 +4532,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
break; break;
case 0x2c: /* frstor mem */ case 0x2c: /* frstor mem */
gen_helper_frstor(cpu_env, s->A0, gen_helper_frstor(cpu_env, s->A0,
tcg_const_i32(dflag - 1)); tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false; update_fip = update_fdp = false;
break; break;
case 0x2e: /* fnsave mem */ case 0x2e: /* fnsave mem */
gen_helper_fsave(cpu_env, s->A0, gen_helper_fsave(cpu_env, s->A0,
tcg_const_i32(dflag - 1)); tcg_constant_i32(dflag - 1));
update_fip = update_fdp = false; update_fip = update_fdp = false;
break; break;
case 0x2f: /* fnstsw mem */ case 0x2f: /* fnstsw mem */
@ -4587,12 +4587,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
case 0x08: /* fld sti */ case 0x08: /* fld sti */
gen_helper_fpush(cpu_env); gen_helper_fpush(cpu_env);
gen_helper_fmov_ST0_STN(cpu_env, gen_helper_fmov_ST0_STN(cpu_env,
tcg_const_i32((opreg + 1) & 7)); tcg_constant_i32((opreg + 1) & 7));
break; break;
case 0x09: /* fxchg sti */ case 0x09: /* fxchg sti */
case 0x29: /* fxchg4 sti, undocumented op */ case 0x29: /* fxchg4 sti, undocumented op */
case 0x39: /* fxchg7 sti, undocumented op */ case 0x39: /* fxchg7 sti, undocumented op */
gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg)); gen_helper_fxchg_ST0_STN(cpu_env, tcg_constant_i32(opreg));
break; break;
case 0x0a: /* grp d9/2 */ case 0x0a: /* grp d9/2 */
switch (rm) { switch (rm) {
@ -4732,27 +4732,27 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
} }
} else { } else {
gen_helper_fmov_FT0_STN(cpu_env, gen_helper_fmov_FT0_STN(cpu_env,
tcg_const_i32(opreg)); tcg_constant_i32(opreg));
gen_helper_fp_arith_ST0_FT0(op1); gen_helper_fp_arith_ST0_FT0(op1);
} }
} }
break; break;
case 0x02: /* fcom */ case 0x02: /* fcom */
case 0x22: /* fcom2, undocumented op */ case 0x22: /* fcom2, undocumented op */
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fcom_ST0_FT0(cpu_env); gen_helper_fcom_ST0_FT0(cpu_env);
break; break;
case 0x03: /* fcomp */ case 0x03: /* fcomp */
case 0x23: /* fcomp3, undocumented op */ case 0x23: /* fcomp3, undocumented op */
case 0x32: /* fcomp5, undocumented op */ case 0x32: /* fcomp5, undocumented op */
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fcom_ST0_FT0(cpu_env); gen_helper_fcom_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env);
break; break;
case 0x15: /* da/5 */ case 0x15: /* da/5 */
switch (rm) { switch (rm) {
case 1: /* fucompp */ case 1: /* fucompp */
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(1));
gen_helper_fucom_ST0_FT0(cpu_env); gen_helper_fucom_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env);
gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env);
@ -4786,7 +4786,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
goto illegal_op; goto illegal_op;
} }
gen_update_cc_op(s); gen_update_cc_op(s);
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fucomi_ST0_FT0(cpu_env); gen_helper_fucomi_ST0_FT0(cpu_env);
set_cc_op(s, CC_OP_EFLAGS); set_cc_op(s, CC_OP_EFLAGS);
break; break;
@ -4795,36 +4795,36 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
goto illegal_op; goto illegal_op;
} }
gen_update_cc_op(s); gen_update_cc_op(s);
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fcomi_ST0_FT0(cpu_env); gen_helper_fcomi_ST0_FT0(cpu_env);
set_cc_op(s, CC_OP_EFLAGS); set_cc_op(s, CC_OP_EFLAGS);
break; break;
case 0x28: /* ffree sti */ case 0x28: /* ffree sti */
gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); gen_helper_ffree_STN(cpu_env, tcg_constant_i32(opreg));
break; break;
case 0x2a: /* fst sti */ case 0x2a: /* fst sti */
gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); gen_helper_fmov_STN_ST0(cpu_env, tcg_constant_i32(opreg));
break; break;
case 0x2b: /* fstp sti */ case 0x2b: /* fstp sti */
case 0x0b: /* fstp1 sti, undocumented op */ case 0x0b: /* fstp1 sti, undocumented op */
case 0x3a: /* fstp8 sti, undocumented op */ case 0x3a: /* fstp8 sti, undocumented op */
case 0x3b: /* fstp9 sti, undocumented op */ case 0x3b: /* fstp9 sti, undocumented op */
gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg)); gen_helper_fmov_STN_ST0(cpu_env, tcg_constant_i32(opreg));
gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env);
break; break;
case 0x2c: /* fucom st(i) */ case 0x2c: /* fucom st(i) */
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fucom_ST0_FT0(cpu_env); gen_helper_fucom_ST0_FT0(cpu_env);
break; break;
case 0x2d: /* fucomp st(i) */ case 0x2d: /* fucomp st(i) */
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fucom_ST0_FT0(cpu_env); gen_helper_fucom_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env);
break; break;
case 0x33: /* de/3 */ case 0x33: /* de/3 */
switch (rm) { switch (rm) {
case 1: /* fcompp */ case 1: /* fcompp */
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1)); gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(1));
gen_helper_fcom_ST0_FT0(cpu_env); gen_helper_fcom_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env);
gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env);
@ -4834,7 +4834,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
} }
break; break;
case 0x38: /* ffreep sti, undocumented op */ case 0x38: /* ffreep sti, undocumented op */
gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg)); gen_helper_ffree_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env);
break; break;
case 0x3c: /* df/4 */ case 0x3c: /* df/4 */
@ -4853,7 +4853,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
goto illegal_op; goto illegal_op;
} }
gen_update_cc_op(s); gen_update_cc_op(s);
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fucomi_ST0_FT0(cpu_env); gen_helper_fucomi_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env);
set_cc_op(s, CC_OP_EFLAGS); set_cc_op(s, CC_OP_EFLAGS);
@ -4863,7 +4863,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
goto illegal_op; goto illegal_op;
} }
gen_update_cc_op(s); gen_update_cc_op(s);
gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg)); gen_helper_fmov_FT0_STN(cpu_env, tcg_constant_i32(opreg));
gen_helper_fcomi_ST0_FT0(cpu_env); gen_helper_fcomi_ST0_FT0(cpu_env);
gen_helper_fpop(cpu_env); gen_helper_fpop(cpu_env);
set_cc_op(s, CC_OP_EFLAGS); set_cc_op(s, CC_OP_EFLAGS);
@ -4886,7 +4886,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1); op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
l1 = gen_new_label(); l1 = gen_new_label();
gen_jcc1_noeob(s, op1, l1); gen_jcc1_noeob(s, op1, l1);
gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg)); gen_helper_fmov_ST0_STN(cpu_env,
tcg_constant_i32(opreg));
gen_set_label(l1); gen_set_label(l1);
} }
break; break;
@ -5092,8 +5093,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (PE(s) && !VM86(s)) { if (PE(s) && !VM86(s)) {
gen_update_cc_op(s); gen_update_cc_op(s);
gen_update_eip_cur(s); gen_update_eip_cur(s);
gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1), gen_helper_lret_protected(cpu_env, tcg_constant_i32(dflag - 1),
tcg_const_i32(val)); tcg_constant_i32(val));
} else { } else {
gen_stack_A0(s); gen_stack_A0(s);
/* pop offset */ /* pop offset */
@ -5120,7 +5121,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (!check_vm86_iopl(s)) { if (!check_vm86_iopl(s)) {
break; break;
} }
gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1)); gen_helper_iret_real(cpu_env, tcg_constant_i32(dflag - 1));
} else { } else {
gen_helper_iret_protected(cpu_env, tcg_constant_i32(dflag - 1), gen_helper_iret_protected(cpu_env, tcg_constant_i32(dflag - 1),
eip_next_i32(s)); eip_next_i32(s));
@ -5509,7 +5510,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (val == 0) { if (val == 0) {
gen_exception(s, EXCP00_DIVZ); gen_exception(s, EXCP00_DIVZ);
} else { } else {
gen_helper_aam(cpu_env, tcg_const_i32(val)); gen_helper_aam(cpu_env, tcg_constant_i32(val));
set_cc_op(s, CC_OP_LOGICB); set_cc_op(s, CC_OP_LOGICB);
} }
break; break;
@ -5517,7 +5518,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (CODE64(s)) if (CODE64(s))
goto illegal_op; goto illegal_op;
val = x86_ldub_code(env, s); val = x86_ldub_code(env, s);
gen_helper_aad(cpu_env, tcg_const_i32(val)); gen_helper_aad(cpu_env, tcg_constant_i32(val));
set_cc_op(s, CC_OP_LOGICB); set_cc_op(s, CC_OP_LOGICB);
break; break;
/************************/ /************************/
@ -5698,7 +5699,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (!PE(s)) { if (!PE(s)) {
gen_exception_gpf(s); gen_exception_gpf(s);
} else { } else {
gen_helper_sysexit(cpu_env, tcg_const_i32(dflag - 1)); gen_helper_sysexit(cpu_env, tcg_constant_i32(dflag - 1));
s->base.is_jmp = DISAS_EOB_ONLY; s->base.is_jmp = DISAS_EOB_ONLY;
} }
break; break;
@ -5717,7 +5718,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
if (!PE(s)) { if (!PE(s)) {
gen_exception_gpf(s); gen_exception_gpf(s);
} else { } else {
gen_helper_sysret(cpu_env, tcg_const_i32(dflag - 1)); gen_helper_sysret(cpu_env, tcg_constant_i32(dflag - 1));
/* condition codes are modified only in long mode */ /* condition codes are modified only in long mode */
if (LMA(s)) { if (LMA(s)) {
set_cc_op(s, CC_OP_EFLAGS); set_cc_op(s, CC_OP_EFLAGS);
@ -5923,7 +5924,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
} }
gen_update_cc_op(s); gen_update_cc_op(s);
gen_update_eip_cur(s); gen_update_eip_cur(s);
gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), gen_helper_vmrun(cpu_env, tcg_constant_i32(s->aflag - 1),
cur_insn_len_i32(s)); cur_insn_len_i32(s));
tcg_gen_exit_tb(NULL, 0); tcg_gen_exit_tb(NULL, 0);
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
@ -5947,7 +5948,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
} }
gen_update_cc_op(s); gen_update_cc_op(s);
gen_update_eip_cur(s); gen_update_eip_cur(s);
gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag - 1)); gen_helper_vmload(cpu_env, tcg_constant_i32(s->aflag - 1));
break; break;
case 0xdb: /* VMSAVE */ case 0xdb: /* VMSAVE */
@ -5959,7 +5960,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
} }
gen_update_cc_op(s); gen_update_cc_op(s);
gen_update_eip_cur(s); gen_update_eip_cur(s);
gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag - 1)); gen_helper_vmsave(cpu_env, tcg_constant_i32(s->aflag - 1));
break; break;
case 0xdc: /* STGI */ case 0xdc: /* STGI */