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target/riscv: Add helper functions to calculate current number of masked bits for pointer masking

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Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250106102346.1100149-4-baturo.alexey@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Alexey Baturo 2025-01-06 13:23:42 +03:00 committed by Alistair Francis
parent 33ca99a111
commit 3d1c5c0885
2 changed files with 83 additions and 0 deletions
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5
target/riscv/cpu.h
View File

@ -772,8 +772,13 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
bool riscv_cpu_is_32bit(RISCVCPU *cpu); bool riscv_cpu_is_32bit(RISCVCPU *cpu);
bool riscv_cpu_virt_mem_enabled(CPURISCVState *env);
RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env);
uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm);
RISCVException riscv_csrr(CPURISCVState *env, int csrno, RISCVException riscv_csrr(CPURISCVState *env, int csrno,
target_ulong *ret_value); target_ulong *ret_value);
RISCVException riscv_csrrw(CPURISCVState *env, int csrno, RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask); target_ulong new_value, target_ulong write_mask);

78
target/riscv/cpu_helper.c
View File

@ -214,6 +214,84 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
*pflags = flags; *pflags = flags;
} }
RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
{
#ifndef CONFIG_USER_ONLY
int priv_mode = cpu_address_mode(env);
if (get_field(env->mstatus, MSTATUS_MPRV) &&
get_field(env->mstatus, MSTATUS_MXR)) {
return PMM_FIELD_DISABLED;
}
/* Get current PMM field */
switch (priv_mode) {
case PRV_M:
if (riscv_cpu_cfg(env)->ext_smmpm) {
return get_field(env->mseccfg, MSECCFG_PMM);
}
break;
case PRV_S:
if (riscv_cpu_cfg(env)->ext_smnpm) {
if (get_field(env->mstatus, MSTATUS_MPV)) {
return get_field(env->henvcfg, HENVCFG_PMM);
} else {
return get_field(env->menvcfg, MENVCFG_PMM);
}
}
break;
case PRV_U:
if (riscv_has_ext(env, RVS)) {
if (riscv_cpu_cfg(env)->ext_ssnpm) {
return get_field(env->senvcfg, SENVCFG_PMM);
}
} else {
if (riscv_cpu_cfg(env)->ext_smnpm) {
return get_field(env->menvcfg, MENVCFG_PMM);
}
}
break;
default:
g_assert_not_reached();
}
return PMM_FIELD_DISABLED;
#else
return PMM_FIELD_DISABLED;
#endif
}
bool riscv_cpu_virt_mem_enabled(CPURISCVState *env)
{
#ifndef CONFIG_USER_ONLY
int satp_mode = 0;
int priv_mode = cpu_address_mode(env);
if (riscv_cpu_mxl(env) == MXL_RV32) {
satp_mode = get_field(env->satp, SATP32_MODE);
} else {
satp_mode = get_field(env->satp, SATP64_MODE);
}
return ((satp_mode != VM_1_10_MBARE) && (priv_mode != PRV_M));
#else
return false;
#endif
}
uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm)
{
switch (pmm) {
case PMM_FIELD_DISABLED:
return 0;
case PMM_FIELD_PMLEN7:
return 7;
case PMM_FIELD_PMLEN16:
return 16;
default:
g_assert_not_reached();
}
}
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
/* /*