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target-arm queue:

Browse Source 
* hw/arm/virt: fix GIC maintenance IRQ registration
  * target/arm: HVC at EL3 should go to EL3, not EL2
  * target/arm: Correct MTE tag checking for reverse-copy MOPS
  * target/arm/tcg: enable PMU feature for Cortex-A8 and A9
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Merge tag 'pull-target-arm-20231113' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * hw/arm/virt: fix GIC maintenance IRQ registration
 * target/arm: HVC at EL3 should go to EL3, not EL2
 * target/arm: Correct MTE tag checking for reverse-copy MOPS
 * target/arm/tcg: enable PMU feature for Cortex-A8 and A9

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# gpg: Signature made Mon 13 Nov 2023 12:45:33 EST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20231113' of https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm/tcg: enable PMU feature for Cortex-A8 and A9
  target/arm: Correct MTE tag checking for reverse-copy MOPS
  target/arm: HVC at EL3 should go to EL3, not EL2
  hw/arm/virt: fix GIC maintenance IRQ registration

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2023-11-14 10:49:01 -05:00
commit 3b06e4058d
4 changed files with 19 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
hw/arm/virt.c
View File

@ -576,7 +576,8 @@ static void fdt_add_gic_node(VirtMachineState *vms)
if (vms->virt) { if (vms->virt) {
qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, GIC_FDT_IRQ_TYPE_PPI,
INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
GIC_FDT_IRQ_FLAGS_LEVEL_HI); GIC_FDT_IRQ_FLAGS_LEVEL_HI);
} }
} else { } else {
@ -600,7 +601,8 @@ static void fdt_add_gic_node(VirtMachineState *vms)
2, vms->memmap[VIRT_GIC_VCPU].base, 2, vms->memmap[VIRT_GIC_VCPU].base,
2, vms->memmap[VIRT_GIC_VCPU].size); 2, vms->memmap[VIRT_GIC_VCPU].size);
qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ, GIC_FDT_IRQ_TYPE_PPI,
INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
GIC_FDT_IRQ_FLAGS_LEVEL_HI); GIC_FDT_IRQ_FLAGS_LEVEL_HI);
} }
} }

2
target/arm/tcg/cpu32.c
View File

@ -351,6 +351,7 @@ static void cortex_a8_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_EL3);
set_feature(&cpu->env, ARM_FEATURE_PMU);
cpu->midr = 0x410fc080; cpu->midr = 0x410fc080;
cpu->reset_fpsid = 0x410330c0; cpu->reset_fpsid = 0x410330c0;
cpu->isar.mvfr0 = 0x11110222; cpu->isar.mvfr0 = 0x11110222;
@ -418,6 +419,7 @@ static void cortex_a9_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_EL3);
set_feature(&cpu->env, ARM_FEATURE_PMU);
/* /*
* Note that A9 supports the MP extensions even for * Note that A9 supports the MP extensions even for
* A9UP and single-core A9MP (which are both different * A9UP and single-core A9MP (which are both different

12
target/arm/tcg/mte_helper.c
View File

@ -1101,10 +1101,18 @@ uint64_t mte_mops_probe_rev(CPUARMState *env, uint64_t ptr, uint64_t size,
uint32_t n; uint32_t n;
mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
/* True probe; this will never fault */ /*
* True probe; this will never fault. Note that our caller passes
* us a pointer to the end of the region, but allocation_tag_mem_probe()
* wants a pointer to the start. Because we know we don't span a page
* boundary and that allocation_tag_mem_probe() doesn't otherwise care
* about the size, pass in a size of 1 byte. This is simpler than
* adjusting the ptr to point to the start of the region and then having
* to adjust the returned 'mem' to get the end of the tag memory.
*/
mem = allocation_tag_mem_probe(env, mmu_idx, ptr, mem = allocation_tag_mem_probe(env, mmu_idx, ptr,
w ? MMU_DATA_STORE : MMU_DATA_LOAD, w ? MMU_DATA_STORE : MMU_DATA_LOAD,
size, MMU_DATA_LOAD, true, 0); 1, MMU_DATA_LOAD, true, 0);
if (!mem) { if (!mem) {
return size; return size;
} }

4
target/arm/tcg/translate-a64.c
View File

@ -2351,6 +2351,8 @@ static bool trans_SVC(DisasContext *s, arg_i *a)
static bool trans_HVC(DisasContext *s, arg_i *a) static bool trans_HVC(DisasContext *s, arg_i *a)
{ {
int target_el = s->current_el == 3 ? 3 : 2;
if (s->current_el == 0) { if (s->current_el == 0) {
unallocated_encoding(s); unallocated_encoding(s);
return true; return true;
@ -2363,7 +2365,7 @@ static bool trans_HVC(DisasContext *s, arg_i *a)
gen_helper_pre_hvc(tcg_env); gen_helper_pre_hvc(tcg_env);
/* Architecture requires ss advance before we do the actual work */ /* Architecture requires ss advance before we do the actual work */
gen_ss_advance(s); gen_ss_advance(s);
gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), 2); gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), target_el);
return true; return true;
} }