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target/x86: Set FloatInfZeroNaNRule explicitly

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Set the FloatInfZeroNaNRule explicitly for the x86 target.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2024-12-11 15:30:55 +00:00
parent 67c0df045e
commit 390df9046b
2 changed files with 8 additions and 1 deletions
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2
fpu/softfloat-specialize.c.inc
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@ -490,7 +490,7 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
* Temporarily fall back to ifdef ladder
*/
#if defined(TARGET_HPPA) || \
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
defined(TARGET_LOONGARCH)
/*
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
* case sets InvalidOp and returns the input value 'c'

7
target/i386/tcg/fpu_helper.c
View File

@ -173,6 +173,13 @@ void cpu_init_fp_statuses(CPUX86State *env)
*/
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status);
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status);
/*
* Only SSE has multiply-add instructions. In the SDM Section 14.5.2
* "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is
* specified -- for 0 * inf + NaN the input NaN is selected, and if
* there are multiple input NaNs they are selected in the order a, b, c.
*/
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
}
static inline uint8_t save_exception_flags(CPUX86State *env)