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* Fix a KVM SMP guest hang. This is not completely trivial, but just

Browse Source 
small enough to merge it. If this causes any more problems, we can
   revert it and the timebase patch which exposed the underlying issue
   for release.
 * Fix a bunch of Coverity issues reported introduced in ppc, mostly in
   powernv code.
 * Fix a NetBSD boot bug on mac99 caused by VSX/VMX decodetree rewrite.
 * Fix the default CPU selection for older spapr machines.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEETkN92lZhb0MpsKeVZ7MCdqhiHK4FAmfdBbsACgkQZ7MCdqhi
 HK50jxAAi38NfsYBXBFSStwQKTBfbuhjDP2A1wiJVDrcJydQXnZb/xCR+kgRdiZt
 I5roIvD2bsbgHJtnCthLo0fQVGPIohsWUnnR6BlEAVN/gwW+8T+tNhLEZZ402+GK
 bzc4pxqtFitS9m5gyAat2g8bfLEEpEmUr2uAJXnPMDDrzSwtbtlUgPKGXfppsyhp
 P26Ut9M6dmPt+EMdJUTJ4RDOPuj53lXmDnbtpG9sA0zYXlG3sRe7nE9X0iKwXB4g
 Yher/IHSyHVqFe3t9TX9m/DY1EU8fFX/GoShoIMLk8v5Sy1viIsUXpWiIn9O3h1E
 WoAS6HvH3CdcHz3EC1XXSGEjEz2r75kPVvLC/wDy4DmXMxSnadodjGohbUkYs+26
 IV/Y3cnGTE2sPoP+vwmv7UKzBncKzTQO2luLkTQzX+x6XGr1MQPdAIm4WW9KfQVq
 VMS06/oqlQQ8gspAWpNo86P+8/hpFlN42dEE+mzARJkm1JNrO+0yMj8OB/og1o92
 T585TOpPDLm8ZeY8fETpgJ0rR4AKb+5e9KnbmS7XuvIWPK/G7OOt5gF8YXiT9yKw
 R77TPm7Evq6zJ9+TQ4KPBqn4LumphXiBWsSpsVcmZqTTf7nKqii0ZdO8asrtn8oN
 pgJ9AgAlnlCUIn4a/sDJ6k/HhC19IxyfC+y4bgsevwGOmo8H43s=
 =SYBy
 -----END PGP SIGNATURE-----

Merge tag 'pull-ppc-for-10.0-2-20250321' of https://gitlab.com/npiggin/qemu into staging

* Fix a KVM SMP guest hang. This is not completely trivial, but just
  small enough to merge it. If this causes any more problems, we can
  revert it and the timebase patch which exposed the underlying issue
  for release.
* Fix a bunch of Coverity issues reported introduced in ppc, mostly in
  powernv code.
* Fix a NetBSD boot bug on mac99 caused by VSX/VMX decodetree rewrite.
* Fix the default CPU selection for older spapr machines.

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCgAdFiEETkN92lZhb0MpsKeVZ7MCdqhiHK4FAmfdBbsACgkQZ7MCdqhi
# HK50jxAAi38NfsYBXBFSStwQKTBfbuhjDP2A1wiJVDrcJydQXnZb/xCR+kgRdiZt
# I5roIvD2bsbgHJtnCthLo0fQVGPIohsWUnnR6BlEAVN/gwW+8T+tNhLEZZ402+GK
# bzc4pxqtFitS9m5gyAat2g8bfLEEpEmUr2uAJXnPMDDrzSwtbtlUgPKGXfppsyhp
# P26Ut9M6dmPt+EMdJUTJ4RDOPuj53lXmDnbtpG9sA0zYXlG3sRe7nE9X0iKwXB4g
# Yher/IHSyHVqFe3t9TX9m/DY1EU8fFX/GoShoIMLk8v5Sy1viIsUXpWiIn9O3h1E
# WoAS6HvH3CdcHz3EC1XXSGEjEz2r75kPVvLC/wDy4DmXMxSnadodjGohbUkYs+26
# IV/Y3cnGTE2sPoP+vwmv7UKzBncKzTQO2luLkTQzX+x6XGr1MQPdAIm4WW9KfQVq
# VMS06/oqlQQ8gspAWpNo86P+8/hpFlN42dEE+mzARJkm1JNrO+0yMj8OB/og1o92
# T585TOpPDLm8ZeY8fETpgJ0rR4AKb+5e9KnbmS7XuvIWPK/G7OOt5gF8YXiT9yKw
# R77TPm7Evq6zJ9+TQ4KPBqn4LumphXiBWsSpsVcmZqTTf7nKqii0ZdO8asrtn8oN
# pgJ9AgAlnlCUIn4a/sDJ6k/HhC19IxyfC+y4bgsevwGOmo8H43s=
# =SYBy
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 21 Mar 2025 02:22:51 EDT
# gpg:                using RSA key 4E437DDA56616F4329B0A79567B30276A8621CAE
# gpg: Good signature from "Nicholas Piggin <npiggin@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4E43 7DDA 5661 6F43 29B0  A795 67B3 0276 A862 1CAE

* tag 'pull-ppc-for-10.0-2-20250321' of https://gitlab.com/npiggin/qemu:
  target/ppc: Fix e200 duplicate SPRs
  target/ppc: Fix facility interrupt checks for VSX
  ppc/spapr: fix default cpu for pre-9.0 machines.
  ppc/amigaone: Constify default_env
  ppc/amigaone: Check blk_pwrite return value
  ppc/pnv: Fix system symbols in HOMER structure definitions
  ppc/pnv: Move the PNOR LPC address into struct PnvPnor
  ppc/spapr: Fix possible pa_features memory overflow
  ppc/xive2: Fix logical / bitwise comparison typo
  pnv/xive: Fix possible undefined shift error in group size calculation
  ppc/xive: Fix typo in crowd block level calculation
  ppc/spapr: Fix RTAS stopped state

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2025-03-23 11:03:33 -04:00
commit 3907add7a6
17 changed files with 194 additions and 146 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
hw/intc/xive.c
View File

@ -1662,12 +1662,20 @@ uint32_t xive_get_vpgroup_size(uint32_t nvp_index)
* (starting with the least significant bits) in the NVP index * (starting with the least significant bits) in the NVP index
* gives the size of the group. * gives the size of the group.
*/ */
return 1 << (ctz32(~nvp_index) + 1); int first_zero = cto32(nvp_index);
if (first_zero >= 31) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid group index 0x%08x",
nvp_index);
return 0;
}
return 1U << (first_zero + 1);
} }
static uint8_t xive_get_group_level(bool crowd, bool ignore, static uint8_t xive_get_group_level(bool crowd, bool ignore,
uint32_t nvp_blk, uint32_t nvp_index) uint32_t nvp_blk, uint32_t nvp_index)
{ {
int first_zero;
uint8_t level; uint8_t level;
if (!ignore) { if (!ignore) {
@ -1675,18 +1683,31 @@ static uint8_t xive_get_group_level(bool crowd, bool ignore,
return 0; return 0;
} }
level = (ctz32(~nvp_index) + 1) & 0b1111; first_zero = cto32(nvp_index);
if (first_zero >= 31) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid group index 0x%08x",
nvp_index);
return 0;
}
level = (first_zero + 1) & 0b1111;
if (crowd) { if (crowd) {
uint32_t blk; uint32_t blk;
/* crowd level is bit position of first 0 from the right in nvp_blk */ /* crowd level is bit position of first 0 from the right in nvp_blk */
blk = ctz32(~nvp_blk) + 1; first_zero = cto32(nvp_blk);
if (first_zero >= 31) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid crowd block 0x%08x",
nvp_blk);
return 0;
}
blk = first_zero + 1;
/* /*
* Supported crowd sizes are 2^1, 2^2, and 2^4. 2^3 is not supported. * Supported crowd sizes are 2^1, 2^2, and 2^4. 2^3 is not supported.
* HW will encode level 4 as the value 3. See xive2_pgofnext(). * HW will encode level 4 as the value 3. See xive2_pgofnext().
*/ */
switch (level) { switch (blk) {
case 1: case 1:
case 2: case 2:
break; break;

21
hw/intc/xive2.c
View File

@ -1153,13 +1153,15 @@ static bool xive2_vp_match_mask(uint32_t cam1, uint32_t cam2,
static uint8_t xive2_get_vp_block_mask(uint32_t nvt_blk, bool crowd) static uint8_t xive2_get_vp_block_mask(uint32_t nvt_blk, bool crowd)
{ {
uint8_t size, block_mask = 0b1111; uint8_t block_mask = 0b1111;
/* 3 supported crowd sizes: 2, 4, 16 */ /* 3 supported crowd sizes: 2, 4, 16 */
if (crowd) { if (crowd) {
size = xive_get_vpgroup_size(nvt_blk); uint32_t size = xive_get_vpgroup_size(nvt_blk);
if (size == 8) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid crowd size of 8n"); if (size != 2 && size != 4 && size != 16) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid crowd size of %d",
size);
return block_mask; return block_mask;
} }
block_mask &= ~(size - 1); block_mask &= ~(size - 1);
@ -1172,7 +1174,14 @@ static uint32_t xive2_get_vp_index_mask(uint32_t nvt_index, bool cam_ignore)
uint32_t index_mask = 0xFFFFFF; /* 24 bits */ uint32_t index_mask = 0xFFFFFF; /* 24 bits */
if (cam_ignore) { if (cam_ignore) {
index_mask &= ~(xive_get_vpgroup_size(nvt_index) - 1); uint32_t size = xive_get_vpgroup_size(nvt_index);
if (size < 2) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid group size of %d",
size);
return index_mask;
}
index_mask &= ~(size - 1);
} }
return index_mask; return index_mask;
} }
@ -1335,7 +1344,7 @@ static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk,
return; return;
} }
if (xive2_end_is_crowd(&end) & !xive2_end_is_ignore(&end)) { if (xive2_end_is_crowd(&end) && !xive2_end_is_ignore(&end)) {
qemu_log_mask(LOG_GUEST_ERROR, qemu_log_mask(LOG_GUEST_ERROR,
"XIVE: invalid END, 'crowd' bit requires 'ignore' bit\n"); "XIVE: invalid END, 'crowd' bit requires 'ignore' bit\n");
return; return;

16
hw/ppc/amigaone.c
View File

@ -63,7 +63,7 @@ static const char dummy_fw[] = {
#define NVRAM_ADDR 0xfd0e0000 #define NVRAM_ADDR 0xfd0e0000
#define NVRAM_SIZE (4 * KiB) #define NVRAM_SIZE (4 * KiB)
static char default_env[] = static const char default_env[] =
"baudrate=115200\0" "baudrate=115200\0"
"stdout=vga\0" "stdout=vga\0"
"stdin=ps2kbd\0" "stdin=ps2kbd\0"
@ -108,8 +108,8 @@ static void nvram_write(void *opaque, hwaddr addr, uint64_t val,
uint8_t *p = memory_region_get_ram_ptr(&s->mr); uint8_t *p = memory_region_get_ram_ptr(&s->mr);
p[addr] = val; p[addr] = val;
if (s->blk) { if (s->blk && blk_pwrite(s->blk, addr, 1, &val, 0) < 0) {
blk_pwrite(s->blk, addr, 1, &val, 0); error_report("%s: could not write %s", __func__, blk_name(s->blk));
} }
} }
@ -151,15 +151,17 @@ static void nvram_realize(DeviceState *dev, Error **errp)
*c = cpu_to_be32(CRC32_DEFAULT_ENV); *c = cpu_to_be32(CRC32_DEFAULT_ENV);
/* Also copies terminating \0 as env is terminated by \0\0 */ /* Also copies terminating \0 as env is terminated by \0\0 */
memcpy(p + 4, default_env, sizeof(default_env)); memcpy(p + 4, default_env, sizeof(default_env));
if (s->blk) { if (s->blk &&
blk_pwrite(s->blk, 0, sizeof(crc) + sizeof(default_env), p, 0); blk_pwrite(s->blk, 0, sizeof(crc) + sizeof(default_env), p, 0) < 0
) {
error_report("%s: could not write %s", __func__, blk_name(s->blk));
} }
return; return;
} }
if (*c == 0) { if (*c == 0) {
*c = cpu_to_be32(crc32(0, p + 4, NVRAM_SIZE - 4)); *c = cpu_to_be32(crc32(0, p + 4, NVRAM_SIZE - 4));
if (s->blk) { if (s->blk && blk_pwrite(s->blk, 0, 4, p, 0) < 0) {
blk_pwrite(s->blk, 0, 4, p, 0); error_report("%s: could not write %s", __func__, blk_name(s->blk));
} }
} }
if (be32_to_cpu(*c) != crc) { if (be32_to_cpu(*c) != crc) {

2
hw/ppc/pnv.c
View File

@ -1191,7 +1191,7 @@ static void pnv_init(MachineState *machine)
* Since we can not reach the remote BMC machine with LPC memops, * Since we can not reach the remote BMC machine with LPC memops,
* map it always for now. * map it always for now.
*/ */
memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, memory_region_add_subregion(pnv->chips[0]->fw_mr, pnv->pnor->lpc_address,
&pnv->pnor->mmio); &pnv->pnor->mmio);
/* /*

4
hw/ppc/pnv_bmc.c
View File

@ -174,8 +174,8 @@ static void hiomap_cmd(IPMIBmcSim *ibs, uint8_t *cmd, unsigned int cmd_len,
{ {
PnvPnor *pnor = PNV_PNOR(object_property_get_link(OBJECT(ibs), "pnor", PnvPnor *pnor = PNV_PNOR(object_property_get_link(OBJECT(ibs), "pnor",
&error_abort)); &error_abort));
uint32_t pnor_addr = pnor->lpc_address;
uint32_t pnor_size = pnor->size; uint32_t pnor_size = pnor->size;
uint32_t pnor_addr = PNOR_SPI_OFFSET;
bool readonly = false; bool readonly = false;
rsp_buffer_push(rsp, cmd[2]); rsp_buffer_push(rsp, cmd[2]);
@ -251,8 +251,8 @@ static const IPMINetfn hiomap_netfn = {
void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor) void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor)
{ {
uint32_t pnor_addr = pnor->lpc_address;
uint32_t pnor_size = pnor->size; uint32_t pnor_size = pnor->size;
uint32_t pnor_addr = PNOR_SPI_OFFSET;
if (!pnv_bmc_is_simulator(bmc)) { if (!pnv_bmc_is_simulator(bmc)) {
return; return;

6
hw/ppc/pnv_core.c
View File

@ -248,21 +248,25 @@ static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr,
if (val & PPC_BIT(7 + 8 * i)) { /* stop */ if (val & PPC_BIT(7 + 8 * i)) { /* stop */
val &= ~PPC_BIT(7 + 8 * i); val &= ~PPC_BIT(7 + 8 * i);
cpu_pause(cs);
env->quiesced = true; env->quiesced = true;
ppc_maybe_interrupt(env);
cpu_pause(cs);
} }
if (val & PPC_BIT(6 + 8 * i)) { /* start */ if (val & PPC_BIT(6 + 8 * i)) { /* start */
val &= ~PPC_BIT(6 + 8 * i); val &= ~PPC_BIT(6 + 8 * i);
env->quiesced = false; env->quiesced = false;
ppc_maybe_interrupt(env);
cpu_resume(cs); cpu_resume(cs);
} }
if (val & PPC_BIT(4 + 8 * i)) { /* sreset */ if (val & PPC_BIT(4 + 8 * i)) { /* sreset */
val &= ~PPC_BIT(4 + 8 * i); val &= ~PPC_BIT(4 + 8 * i);
env->quiesced = false; env->quiesced = false;
ppc_maybe_interrupt(env);
pnv_cpu_do_nmi_resume(cs); pnv_cpu_do_nmi_resume(cs);
} }
if (val & PPC_BIT(3 + 8 * i)) { /* clear maint */ if (val & PPC_BIT(3 + 8 * i)) { /* clear maint */
env->quiesced = false; env->quiesced = false;
ppc_maybe_interrupt(env);
/* /*
* Hardware has very particular cases for where clear maint * Hardware has very particular cases for where clear maint
* must be used and where start must be used to resume a * must be used and where start must be used to resume a

201
hw/ppc/pnv_occ.c
View File

@ -364,7 +364,12 @@ static void pnv_occ_register_types(void)
type_init(pnv_occ_register_types); type_init(pnv_occ_register_types);
/* From skiboot/hw/occ.c with tab to space conversion */ /*
* From skiboot/hw/occ.c with following changes:
* - tab to space conversion
* - Type conversions u8->uint8_t s8->int8_t __be16->uint16_t etc
* - __packed -> QEMU_PACKED
*/
/* OCC Communication Area for PStates */ /* OCC Communication Area for PStates */
#define OPAL_DYNAMIC_DATA_OFFSET 0x0B80 #define OPAL_DYNAMIC_DATA_OFFSET 0x0B80
@ -384,20 +389,6 @@ type_init(pnv_occ_register_types);
#define FREQ_MAX_IN_DOMAIN 0 #define FREQ_MAX_IN_DOMAIN 0
#define FREQ_MOST_RECENTLY_SET 1 #define FREQ_MOST_RECENTLY_SET 1
#define u8 uint8_t
#define s8 int8_t
#define u16 uint16_t
#define s16 int16_t
#define u32 uint32_t
#define s32 int32_t
#define u64 uint64_t
#define s64 int64_t
#define __be16 uint16_t
#define __be32 uint32_t
#ifndef __packed
#define __packed QEMU_PACKED
#endif /* !__packed */
/** /**
* OCC-OPAL Shared Memory Region * OCC-OPAL Shared Memory Region
* *
@ -434,69 +425,69 @@ type_init(pnv_occ_register_types);
* @spare/reserved/pad: Unused data * @spare/reserved/pad: Unused data
*/ */
struct occ_pstate_table { struct occ_pstate_table {
u8 valid; uint8_t valid;
u8 version; uint8_t version;
union __packed { union QEMU_PACKED {
struct __packed { /* Version 0x01 and 0x02 */ struct QEMU_PACKED { /* Version 0x01 and 0x02 */
u8 throttle; uint8_t throttle;
s8 pstate_min; int8_t pstate_min;
s8 pstate_nom; int8_t pstate_nom;
s8 pstate_turbo; int8_t pstate_turbo;
s8 pstate_ultra_turbo; int8_t pstate_ultra_turbo;
u8 spare; uint8_t spare;
u64 reserved; uint64_t reserved;
struct __packed { struct QEMU_PACKED {
s8 id; int8_t id;
u8 flags; uint8_t flags;
u8 vdd; uint8_t vdd;
u8 vcs; uint8_t vcs;
__be32 freq_khz; uint32_t freq_khz;
} pstates[MAX_PSTATES]; } pstates[MAX_PSTATES];
s8 core_max[MAX_P8_CORES]; int8_t core_max[MAX_P8_CORES];
u8 pad[100]; uint8_t pad[100];
} v2; } v2;
struct __packed { /* Version 0x90 */ struct QEMU_PACKED { /* Version 0x90 */
u8 occ_role; uint8_t occ_role;
u8 pstate_min; uint8_t pstate_min;
u8 pstate_nom; uint8_t pstate_nom;
u8 pstate_turbo; uint8_t pstate_turbo;
u8 pstate_ultra_turbo; uint8_t pstate_ultra_turbo;
u8 spare; uint8_t spare;
u64 reserved1; uint64_t reserved1;
u64 reserved2; uint64_t reserved2;
struct __packed { struct QEMU_PACKED {
u8 id; uint8_t id;
u8 flags; uint8_t flags;
u16 reserved; uint16_t reserved;
__be32 freq_khz; uint32_t freq_khz;
} pstates[MAX_PSTATES]; } pstates[MAX_PSTATES];
u8 core_max[MAX_P9_CORES]; uint8_t core_max[MAX_P9_CORES];
u8 pad[56]; uint8_t pad[56];
} v9; } v9;
struct __packed { /* Version 0xA0 */ struct QEMU_PACKED { /* Version 0xA0 */
u8 occ_role; uint8_t occ_role;
u8 pstate_min; uint8_t pstate_min;
u8 pstate_fixed_freq; uint8_t pstate_fixed_freq;
u8 pstate_base; uint8_t pstate_base;
u8 pstate_ultra_turbo; uint8_t pstate_ultra_turbo;
u8 pstate_fmax; uint8_t pstate_fmax;
u8 minor; uint8_t minor;
u8 pstate_bottom_throttle; uint8_t pstate_bottom_throttle;
u8 spare; uint8_t spare;
u8 spare1; uint8_t spare1;
u32 reserved_32; uint32_t reserved_32;
u64 reserved_64; uint64_t reserved_64;
struct __packed { struct QEMU_PACKED {
u8 id; uint8_t id;
u8 valid; uint8_t valid;
u16 reserved; uint16_t reserved;
__be32 freq_khz; uint32_t freq_khz;
} pstates[MAX_PSTATES]; } pstates[MAX_PSTATES];
u8 core_max[MAX_P10_CORES]; uint8_t core_max[MAX_P10_CORES];
u8 pad[48]; uint8_t pad[48];
} v10; } v10;
}; };
} __packed; } QEMU_PACKED;
/** /**
* OPAL-OCC Command Response Interface * OPAL-OCC Command Response Interface
@ -531,13 +522,13 @@ struct occ_pstate_table {
* @spare: Unused byte * @spare: Unused byte
*/ */
struct opal_command_buffer { struct opal_command_buffer {
u8 flag; uint8_t flag;
u8 request_id; uint8_t request_id;
u8 cmd; uint8_t cmd;
u8 spare; uint8_t spare;
__be16 data_size; uint16_t data_size;
u8 data[MAX_OPAL_CMD_DATA_LENGTH]; uint8_t data[MAX_OPAL_CMD_DATA_LENGTH];
} __packed; } QEMU_PACKED;
/** /**
* OPAL-OCC Response Buffer * OPAL-OCC Response Buffer
@ -571,13 +562,13 @@ struct opal_command_buffer {
* @data: Response specific data * @data: Response specific data
*/ */
struct occ_response_buffer { struct occ_response_buffer {
u8 flag; uint8_t flag;
u8 request_id; uint8_t request_id;
u8 cmd; uint8_t cmd;
u8 status; uint8_t status;
__be16 data_size; uint16_t data_size;
u8 data[MAX_OCC_RSP_DATA_LENGTH]; uint8_t data[MAX_OCC_RSP_DATA_LENGTH];
} __packed; } QEMU_PACKED;
/** /**
* OCC-OPAL Shared Memory Interface Dynamic Data Vx90 * OCC-OPAL Shared Memory Interface Dynamic Data Vx90
@ -608,31 +599,31 @@ struct occ_response_buffer {
* @rsp: OCC Response Buffer * @rsp: OCC Response Buffer
*/ */
struct occ_dynamic_data { struct occ_dynamic_data {
u8 occ_state; uint8_t occ_state;
u8 major_version; uint8_t major_version;
u8 minor_version; uint8_t minor_version;
u8 gpus_present; uint8_t gpus_present;
union __packed { union QEMU_PACKED {
struct __packed { /* Version 0x90 */ struct QEMU_PACKED { /* Version 0x90 */
u8 spare1; uint8_t spare1;
} v9; } v9;
struct __packed { /* Version 0xA0 */ struct QEMU_PACKED { /* Version 0xA0 */
u8 wof_enabled; uint8_t wof_enabled;
} v10; } v10;
}; };
u8 cpu_throttle; uint8_t cpu_throttle;
u8 mem_throttle; uint8_t mem_throttle;
u8 quick_pwr_drop; uint8_t quick_pwr_drop;
u8 pwr_shifting_ratio; uint8_t pwr_shifting_ratio;
u8 pwr_cap_type; uint8_t pwr_cap_type;
__be16 hard_min_pwr_cap; uint16_t hard_min_pwr_cap;
__be16 max_pwr_cap; uint16_t max_pwr_cap;
__be16 cur_pwr_cap; uint16_t cur_pwr_cap;
__be16 soft_min_pwr_cap; uint16_t soft_min_pwr_cap;
u8 pad[110]; uint8_t pad[110];
struct opal_command_buffer cmd; struct opal_command_buffer cmd;
struct occ_response_buffer rsp; struct occ_response_buffer rsp;
} __packed; } QEMU_PACKED;
enum occ_response_status { enum occ_response_status {
OCC_RSP_SUCCESS = 0x00, OCC_RSP_SUCCESS = 0x00,

2
hw/ppc/pnv_pnor.c
View File

@ -108,6 +108,8 @@ static void pnv_pnor_realize(DeviceState *dev, Error **errp)
memset(s->storage, 0xFF, s->size); memset(s->storage, 0xFF, s->size);
} }
s->lpc_address = PNOR_SPI_OFFSET;
memory_region_init_io(&s->mmio, OBJECT(s), &pnv_pnor_ops, s, memory_region_init_io(&s->mmio, OBJECT(s), &pnv_pnor_ops, s,
TYPE_PNV_PNOR, s->size); TYPE_PNV_PNOR, s->size);
} }

2
hw/ppc/spapr.c
View File

@ -296,6 +296,7 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
pa_features[40 + 2] &= ~0x80; /* Radix MMU */ pa_features[40 + 2] &= ~0x80; /* Radix MMU */
} }
if (spapr_get_cap(spapr, SPAPR_CAP_DAWR1)) { if (spapr_get_cap(spapr, SPAPR_CAP_DAWR1)) {
g_assert(pa_size > 66);
pa_features[66] |= 0x80; pa_features[66] |= 0x80;
} }
@ -4815,6 +4816,7 @@ static void spapr_machine_8_2_class_options(MachineClass *mc)
{ {
spapr_machine_9_0_class_options(mc); spapr_machine_9_0_class_options(mc);
compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2");
} }
DEFINE_SPAPR_MACHINE(8, 2); DEFINE_SPAPR_MACHINE(8, 2);

6
hw/ppc/spapr_cpu_core.c
View File

@ -37,6 +37,9 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu)
cpu_reset(cs); cpu_reset(cs);
env->quiesced = true; /* set "RTAS stopped" state. */
ppc_maybe_interrupt(env);
/* /*
* "PowerPC Processor binding to IEEE 1275" defines the initial MSR state * "PowerPC Processor binding to IEEE 1275" defines the initial MSR state
* as 32bit (MSR_SF=0) with MSR_ME=1 and MSR_FP=1 in "8.2.1. Initial * as 32bit (MSR_SF=0) with MSR_ME=1 and MSR_FP=1 in "8.2.1. Initial
@ -98,6 +101,9 @@ void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip,
CPU(cpu)->halted = 0; CPU(cpu)->halted = 0;
/* Enable Power-saving mode Exit Cause exceptions */ /* Enable Power-saving mode Exit Cause exceptions */
ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
env->quiesced = false; /* clear "RTAS stopped" state. */
ppc_maybe_interrupt(env);
} }
/* /*

5
hw/ppc/spapr_rtas.c
View File

@ -110,7 +110,8 @@ static void rtas_query_cpu_stopped_state(PowerPCCPU *cpu_,
id = rtas_ld(args, 0); id = rtas_ld(args, 0);
cpu = spapr_find_cpu(id); cpu = spapr_find_cpu(id);
if (cpu != NULL) { if (cpu != NULL) {
if (CPU(cpu)->halted) { CPUPPCState *env = &cpu->env;
if (env->quiesced) {
rtas_st(rets, 1, 0); rtas_st(rets, 1, 0);
} else { } else {
rtas_st(rets, 1, 2); rtas_st(rets, 1, 2);
@ -215,6 +216,8 @@ static void rtas_stop_self(PowerPCCPU *cpu, SpaprMachineState *spapr,
* For the same reason, set PSSCR_EC. * For the same reason, set PSSCR_EC.
*/ */
env->spr[SPR_PSSCR] |= PSSCR_EC; env->spr[SPR_PSSCR] |= PSSCR_EC;
env->quiesced = true; /* set "RTAS stopped" state. */
ppc_maybe_interrupt(env);
cs->halted = 1; cs->halted = 1;
ppc_store_lpcr(cpu, env->spr[SPR_LPCR] & ~pcc->lpcr_pm); ppc_store_lpcr(cpu, env->spr[SPR_LPCR] & ~pcc->lpcr_pm);
kvmppc_set_reg_ppc_online(cpu, 0); kvmppc_set_reg_ppc_online(cpu, 0);

1
include/hw/ppc/pnv_pnor.h
View File

@ -28,6 +28,7 @@ struct PnvPnor {
BlockBackend *blk; BlockBackend *blk;
uint8_t *storage; uint8_t *storage;
uint32_t lpc_address; /* Offset within LPC FW space */
int64_t size; int64_t size;
MemoryRegion mmio; MemoryRegion mmio;
}; };

11
target/ppc/cpu.h
View File

@ -1356,6 +1356,17 @@ struct CPUArchState {
* special way (such as routing some resume causes to 0x100, i.e. sreset). * special way (such as routing some resume causes to 0x100, i.e. sreset).
*/ */
bool resume_as_sreset; bool resume_as_sreset;
/*
* On powernv, quiesced means the CPU has been stopped using PC direct
* control xscom registers.
*
* On spapr, quiesced means it is in the "RTAS stopped" state.
*
* The core halted/stopped variables aren't sufficient for this, because
* they can be changed with various side-band operations like qmp cont,
* powersave interrupts, etc.
*/
bool quiesced; bool quiesced;
#endif #endif

8
target/ppc/cpu_init.c
View File

@ -2744,14 +2744,6 @@ static void init_proc_e200(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic, &spr_read_generic, &spr_write_generic,
0x00000000); /* TOFIX */ 0x00000000); /* TOFIX */
spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
init_tlbs_emb(env); init_tlbs_emb(env);
init_excp_e200(env, 0xFFFF0000UL); init_excp_e200(env, 0xFFFF0000UL);

4
target/ppc/excp_helper.c
View File

@ -1951,6 +1951,10 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *env)
target_ulong lpcr = env->spr[SPR_LPCR]; target_ulong lpcr = env->spr[SPR_LPCR];
bool async_deliver; bool async_deliver;
if (unlikely(env->quiesced)) {
return 0;
}
#ifdef TARGET_PPC64 #ifdef TARGET_PPC64
switch (env->excp_model) { switch (env->excp_model) {
case POWERPC_EXCP_POWER7: case POWERPC_EXCP_POWER7:

2
target/ppc/translate/vmx-impl.c.inc
View File

@ -994,8 +994,8 @@ static bool do_vector_rotl_quad(DisasContext *ctx, arg_VX *a, bool mask,
{ {
TCGv_i64 ah, al, vrb, n, t0, t1, zero = tcg_constant_i64(0); TCGv_i64 ah, al, vrb, n, t0, t1, zero = tcg_constant_i64(0);
REQUIRE_VECTOR(ctx);
REQUIRE_INSNS_FLAGS2(ctx, ISA310); REQUIRE_INSNS_FLAGS2(ctx, ISA310);
REQUIRE_VECTOR(ctx);
ah = tcg_temp_new_i64(); ah = tcg_temp_new_i64();
al = tcg_temp_new_i64(); al = tcg_temp_new_i64();

20
target/ppc/translate/vsx-impl.c.inc
View File

@ -61,8 +61,8 @@ static bool trans_LXVD2X(DisasContext *ctx, arg_LXVD2X *a)
TCGv EA; TCGv EA;
TCGv_i64 t0; TCGv_i64 t0;
REQUIRE_VSX(ctx);
REQUIRE_INSNS_FLAGS2(ctx, VSX); REQUIRE_INSNS_FLAGS2(ctx, VSX);
REQUIRE_VSX(ctx);
t0 = tcg_temp_new_i64(); t0 = tcg_temp_new_i64();
gen_set_access_type(ctx, ACCESS_INT); gen_set_access_type(ctx, ACCESS_INT);
@ -80,8 +80,8 @@ static bool trans_LXVW4X(DisasContext *ctx, arg_LXVW4X *a)
TCGv EA; TCGv EA;
TCGv_i64 xth, xtl; TCGv_i64 xth, xtl;
REQUIRE_VSX(ctx);
REQUIRE_INSNS_FLAGS2(ctx, VSX); REQUIRE_INSNS_FLAGS2(ctx, VSX);
REQUIRE_VSX(ctx);
xth = tcg_temp_new_i64(); xth = tcg_temp_new_i64();
xtl = tcg_temp_new_i64(); xtl = tcg_temp_new_i64();
@ -113,12 +113,12 @@ static bool trans_LXVWSX(DisasContext *ctx, arg_LXVWSX *a)
TCGv EA; TCGv EA;
TCGv_i32 data; TCGv_i32 data;
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
if (a->rt < 32) { if (a->rt < 32) {
REQUIRE_VSX(ctx); REQUIRE_VSX(ctx);
} else { } else {
REQUIRE_VECTOR(ctx); REQUIRE_VECTOR(ctx);
} }
REQUIRE_INSNS_FLAGS2(ctx, ISA300);
gen_set_access_type(ctx, ACCESS_INT); gen_set_access_type(ctx, ACCESS_INT);
EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
@ -133,8 +133,8 @@ static bool trans_LXVDSX(DisasContext *ctx, arg_LXVDSX *a)
TCGv EA; TCGv EA;
TCGv_i64 data; TCGv_i64 data;
REQUIRE_VSX(ctx);
REQUIRE_INSNS_FLAGS2(ctx, VSX); REQUIRE_INSNS_FLAGS2(ctx, VSX);
REQUIRE_VSX(ctx);
gen_set_access_type(ctx, ACCESS_INT); gen_set_access_type(ctx, ACCESS_INT);
EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]); EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
@ -185,8 +185,8 @@ static bool trans_LXVH8X(DisasContext *ctx, arg_LXVH8X *a)
TCGv EA; TCGv EA;
TCGv_i64 xth, xtl; TCGv_i64 xth, xtl;
REQUIRE_VSX(ctx);
REQUIRE_INSNS_FLAGS2(ctx, ISA300); REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_VSX(ctx);
xth = tcg_temp_new_i64(); xth = tcg_temp_new_i64();
xtl = tcg_temp_new_i64(); xtl = tcg_temp_new_i64();
@ -208,8 +208,8 @@ static bool trans_LXVB16X(DisasContext *ctx, arg_LXVB16X *a)
TCGv EA; TCGv EA;
TCGv_i128 data; TCGv_i128 data;
REQUIRE_VSX(ctx);
REQUIRE_INSNS_FLAGS2(ctx, ISA300); REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_VSX(ctx);
data = tcg_temp_new_i128(); data = tcg_temp_new_i128();
gen_set_access_type(ctx, ACCESS_INT); gen_set_access_type(ctx, ACCESS_INT);
@ -312,8 +312,8 @@ static bool trans_STXVD2X(DisasContext *ctx, arg_STXVD2X *a)
TCGv EA; TCGv EA;
TCGv_i64 t0; TCGv_i64 t0;
REQUIRE_VSX(ctx);
REQUIRE_INSNS_FLAGS2(ctx, VSX); REQUIRE_INSNS_FLAGS2(ctx, VSX);
REQUIRE_VSX(ctx);
t0 = tcg_temp_new_i64(); t0 = tcg_temp_new_i64();
gen_set_access_type(ctx, ACCESS_INT); gen_set_access_type(ctx, ACCESS_INT);
@ -331,8 +331,8 @@ static bool trans_STXVW4X(DisasContext *ctx, arg_STXVW4X *a)
TCGv EA; TCGv EA;
TCGv_i64 xsh, xsl; TCGv_i64 xsh, xsl;
REQUIRE_VSX(ctx);
REQUIRE_INSNS_FLAGS2(ctx, VSX); REQUIRE_INSNS_FLAGS2(ctx, VSX);
REQUIRE_VSX(ctx);
xsh = tcg_temp_new_i64(); xsh = tcg_temp_new_i64();
xsl = tcg_temp_new_i64(); xsl = tcg_temp_new_i64();
@ -364,8 +364,8 @@ static bool trans_STXVH8X(DisasContext *ctx, arg_STXVH8X *a)
TCGv EA; TCGv EA;
TCGv_i64 xsh, xsl; TCGv_i64 xsh, xsl;
REQUIRE_VSX(ctx);
REQUIRE_INSNS_FLAGS2(ctx, ISA300); REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_VSX(ctx);
xsh = tcg_temp_new_i64(); xsh = tcg_temp_new_i64();
xsl = tcg_temp_new_i64(); xsl = tcg_temp_new_i64();
@ -394,8 +394,8 @@ static bool trans_STXVB16X(DisasContext *ctx, arg_STXVB16X *a)
TCGv EA; TCGv EA;
TCGv_i128 data; TCGv_i128 data;
REQUIRE_VSX(ctx);
REQUIRE_INSNS_FLAGS2(ctx, ISA300); REQUIRE_INSNS_FLAGS2(ctx, ISA300);
REQUIRE_VSX(ctx);
data = tcg_temp_new_i128(); data = tcg_temp_new_i128();
gen_set_access_type(ctx, ACCESS_INT); gen_set_access_type(ctx, ACCESS_INT);