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target/i386: do not use gen_op_jz_ecx for repeated string operations

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Explicitly generate a TSTEQ branch (which is optimized to NE x,0 if possible).
This does not make much sense yet, but later we will add more checks and some
will use a temporary to check on the decremented value of CX/ECX/RCX; it will
be clearer for all checks to share the same logic using TSTEQ(reg, cx_mask).

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Link: https://lore.kernel.org/r/20241215090613.89588-10-pbonzini@redhat.com
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2024-12-15 10:06:08 +01:00
parent 6986cf0032
commit 3658116025
1 changed files with 2 additions and 1 deletions
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target/i386/tcg/translate.c
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@ -1338,6 +1338,7 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
bool is_repz_nz)
{
TCGLabel *done = gen_new_label();
target_ulong cx_mask = MAKE_64BIT_MASK(0, 8 << s->aflag);
bool had_rf = s->flags & HF_RF_MASK;
/*
@ -1360,7 +1361,7 @@ static void do_gen_rep(DisasContext *s, MemOp ot,
tcg_set_insn_start_param(s->base.insn_start, 1, CC_OP_DYNAMIC);
/* Any iteration at all? */
gen_op_jz_ecx(s, done);
tcg_gen_brcondi_tl(TCG_COND_TSTEQ, cpu_regs[R_ECX], cx_mask, done);
fn(s, ot);
gen_op_add_reg_im(s, s->aflag, R_ECX, -1);