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target/arm: Use tcg_constant_i64() in do_sat_addsub_64()

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The immediate value used for comparison is constant and
read-only. Move it to the constant pool. This frees a
TCG temporary for unsigned saturation opcodes.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211029231834.2476117-5-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-10-30 01:18:33 +02:00 committed by Richard Henderson
parent cacb1aa486
commit 35a1ec8e47
1 changed files with 8 additions and 9 deletions
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17
target/arm/translate-sve.c
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@ -1943,20 +1943,20 @@ static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
static void do_sat_addsub_64(TCGv_i64 reg, TCGv_i64 val, bool u, bool d) static void do_sat_addsub_64(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
{ {
TCGv_i64 t0 = tcg_temp_new_i64(); TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
TCGv_i64 t2; TCGv_i64 t2;
if (u) { if (u) {
if (d) { if (d) {
tcg_gen_sub_i64(t0, reg, val); tcg_gen_sub_i64(t0, reg, val);
tcg_gen_movi_i64(t1, 0); t2 = tcg_constant_i64(0);
tcg_gen_movcond_i64(TCG_COND_LTU, reg, reg, val, t1, t0); tcg_gen_movcond_i64(TCG_COND_LTU, reg, reg, val, t2, t0);
} else { } else {
tcg_gen_add_i64(t0, reg, val); tcg_gen_add_i64(t0, reg, val);
tcg_gen_movi_i64(t1, -1); t2 = tcg_constant_i64(-1);
tcg_gen_movcond_i64(TCG_COND_LTU, reg, t0, reg, t1, t0); tcg_gen_movcond_i64(TCG_COND_LTU, reg, t0, reg, t2, t0);
} }
} else { } else {
TCGv_i64 t1 = tcg_temp_new_i64();
if (d) { if (d) {
/* Detect signed overflow for subtraction. */ /* Detect signed overflow for subtraction. */
tcg_gen_xor_i64(t0, reg, val); tcg_gen_xor_i64(t0, reg, val);
@ -1966,7 +1966,7 @@ static void do_sat_addsub_64(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
/* Bound the result. */ /* Bound the result. */
tcg_gen_movi_i64(reg, INT64_MIN); tcg_gen_movi_i64(reg, INT64_MIN);
t2 = tcg_const_i64(0); t2 = tcg_constant_i64(0);
tcg_gen_movcond_i64(TCG_COND_LT, reg, t0, t2, reg, t1); tcg_gen_movcond_i64(TCG_COND_LT, reg, t0, t2, reg, t1);
} else { } else {
/* Detect signed overflow for addition. */ /* Detect signed overflow for addition. */
@ -1977,13 +1977,12 @@ static void do_sat_addsub_64(TCGv_i64 reg, TCGv_i64 val, bool u, bool d)
/* Bound the result. */ /* Bound the result. */
tcg_gen_movi_i64(t1, INT64_MAX); tcg_gen_movi_i64(t1, INT64_MAX);
t2 = tcg_const_i64(0); t2 = tcg_constant_i64(0);
tcg_gen_movcond_i64(TCG_COND_LT, reg, t0, t2, t1, reg); tcg_gen_movcond_i64(TCG_COND_LT, reg, t0, t2, t1, reg);
} }
tcg_temp_free_i64(t2); tcg_temp_free_i64(t1);
} }
tcg_temp_free_i64(t0); tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
} }
/* Similarly with a vector and a scalar operand. */ /* Similarly with a vector and a scalar operand. */