SYS-OSS/FRET-qemu
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

target/riscv: Add Smrnmi mnret instruction

Browse Source 
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250106054336.1878291-5-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Tommy Wu 2025-01-06 13:43:34 +08:00 committed by Alistair Francis
parent c1149f69ab
commit 3157a553ec
4 changed files with 64 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
target/riscv/helper.h
View File

@ -131,6 +131,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_1(sret, tl, env)
DEF_HELPER_1(mret, tl, env)
DEF_HELPER_1(mnret, tl, env)
DEF_HELPER_1(wfi, void, env)
DEF_HELPER_1(wrs_nto, void, env)
DEF_HELPER_1(tlb_flush, void, env)

3
target/riscv/insn32.decode
View File

@ -121,6 +121,9 @@ wfi 0001000 00101 00000 000 00000 1110011
sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
# *** NMI ***
mnret 0111000 00010 00000 000 00000 1110011
# *** RV32I Base Instruction Set ***
lui .................... ..... 0110111 @u
{

20
target/riscv/insn_trans/trans_privileged.c.inc
View File

@ -18,6 +18,12 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#define REQUIRE_SMRNMI(ctx) do { \
if (!ctx->cfg_ptr->ext_smrnmi) { \
return false; \
} \
} while (0)
static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
{
/* always generates U-level ECALL, fixed in do_interrupt handler */
@ -106,6 +112,20 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
#endif
}
static bool trans_mnret(DisasContext *ctx, arg_mnret *a)
{
#ifndef CONFIG_USER_ONLY
REQUIRE_SMRNMI(ctx);
decode_save_opc(ctx, 0);
gen_helper_mnret(cpu_pc, tcg_env);
tcg_gen_exit_tb(NULL, 0); /* no chaining */
ctx->base.is_jmp = DISAS_NORETURN;
return true;
#else
return false;
#endif
}
static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
{
#ifndef CONFIG_USER_ONLY

45
target/riscv/op_helper.c
View File

@ -328,24 +328,30 @@ target_ulong helper_sret(CPURISCVState *env)
return retpc;
}
target_ulong helper_mret(CPURISCVState *env)
static void check_ret_from_m_mode(CPURISCVState *env, target_ulong retpc,
target_ulong prev_priv)
{
if (!(env->priv >= PRV_M)) {
riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
}
target_ulong retpc = env->mepc;
if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) {
riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}
uint64_t mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
if (riscv_cpu_cfg(env)->pmp &&
!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
}
}
target_ulong helper_mret(CPURISCVState *env)
{
target_ulong retpc = env->mepc;
uint64_t mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
check_ret_from_m_mode(env, retpc, prev_priv);
target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV) &&
(prev_priv != PRV_M);
@ -377,6 +383,35 @@ target_ulong helper_mret(CPURISCVState *env)
return retpc;
}
target_ulong helper_mnret(CPURISCVState *env)
{
target_ulong retpc = env->mnepc;
target_ulong prev_priv = get_field(env->mnstatus, MNSTATUS_MNPP);
target_ulong prev_virt;
check_ret_from_m_mode(env, retpc, prev_priv);
prev_virt = get_field(env->mnstatus, MNSTATUS_MNPV) &&
(prev_priv != PRV_M);
env->mnstatus = set_field(env->mnstatus, MNSTATUS_NMIE, true);
/*
* If MNRET changes the privilege mode to a mode
* less privileged than M, it also sets mstatus.MPRV to 0.
*/
if (prev_priv < PRV_M) {
env->mstatus = set_field(env->mstatus, MSTATUS_MPRV, false);
}
if (riscv_has_ext(env, RVH) && prev_virt) {
riscv_cpu_swap_hypervisor_regs(env);
}
riscv_cpu_set_mode(env, prev_priv, prev_virt);
return retpc;
}
void helper_wfi(CPURISCVState *env)
{
CPUState *cs = env_cpu(env);