target/arm: Move arm_excp_unmasked to cpu.c
This inline function has one user in cpu.c, and need not be exposed otherwise. Code movement only, with fixups for checkpatch. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200206105448.4726-39-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
cd3f80aba0
commit
310cedf39d
119
target/arm/cpu.c
119
target/arm/cpu.c
@ -410,6 +410,125 @@ static void arm_cpu_reset(CPUState *s)
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arm_rebuild_hflags(env);
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arm_rebuild_hflags(env);
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}
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}
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static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
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unsigned int target_el)
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{
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CPUARMState *env = cs->env_ptr;
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unsigned int cur_el = arm_current_el(env);
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bool secure = arm_is_secure(env);
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bool pstate_unmasked;
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int8_t unmasked = 0;
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uint64_t hcr_el2;
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/*
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* Don't take exceptions if they target a lower EL.
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* This check should catch any exceptions that would not be taken
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* but left pending.
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*/
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if (cur_el > target_el) {
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return false;
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}
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hcr_el2 = arm_hcr_el2_eff(env);
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switch (excp_idx) {
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case EXCP_FIQ:
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pstate_unmasked = !(env->daif & PSTATE_F);
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break;
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case EXCP_IRQ:
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pstate_unmasked = !(env->daif & PSTATE_I);
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break;
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case EXCP_VFIQ:
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if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
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/* VFIQs are only taken when hypervized and non-secure. */
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return false;
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}
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return !(env->daif & PSTATE_F);
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case EXCP_VIRQ:
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if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
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/* VIRQs are only taken when hypervized and non-secure. */
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return false;
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}
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return !(env->daif & PSTATE_I);
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default:
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g_assert_not_reached();
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}
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/*
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* Use the target EL, current execution state and SCR/HCR settings to
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* determine whether the corresponding CPSR bit is used to mask the
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* interrupt.
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*/
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if ((target_el > cur_el) && (target_el != 1)) {
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/* Exceptions targeting a higher EL may not be maskable */
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if (arm_feature(env, ARM_FEATURE_AARCH64)) {
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/*
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* 64-bit masking rules are simple: exceptions to EL3
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* can't be masked, and exceptions to EL2 can only be
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* masked from Secure state. The HCR and SCR settings
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* don't affect the masking logic, only the interrupt routing.
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*/
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if (target_el == 3 || !secure) {
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unmasked = 1;
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}
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} else {
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/*
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* The old 32-bit-only environment has a more complicated
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* masking setup. HCR and SCR bits not only affect interrupt
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* routing but also change the behaviour of masking.
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*/
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bool hcr, scr;
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switch (excp_idx) {
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case EXCP_FIQ:
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/*
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* If FIQs are routed to EL3 or EL2 then there are cases where
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* we override the CPSR.F in determining if the exception is
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* masked or not. If neither of these are set then we fall back
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* to the CPSR.F setting otherwise we further assess the state
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* below.
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*/
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hcr = hcr_el2 & HCR_FMO;
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scr = (env->cp15.scr_el3 & SCR_FIQ);
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/*
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* When EL3 is 32-bit, the SCR.FW bit controls whether the
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* CPSR.F bit masks FIQ interrupts when taken in non-secure
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* state. If SCR.FW is set then FIQs can be masked by CPSR.F
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* when non-secure but only when FIQs are only routed to EL3.
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*/
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scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
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break;
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case EXCP_IRQ:
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/*
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* When EL3 execution state is 32-bit, if HCR.IMO is set then
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* we may override the CPSR.I masking when in non-secure state.
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* The SCR.IRQ setting has already been taken into consideration
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* when setting the target EL, so it does not have a further
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* affect here.
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*/
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hcr = hcr_el2 & HCR_IMO;
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scr = false;
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break;
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default:
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g_assert_not_reached();
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}
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if ((scr || hcr) && !secure) {
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unmasked = 1;
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}
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}
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}
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/*
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* The PSTATE bits only mask the interrupt if we have not overriden the
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* ability above.
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*/
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return unmasked || pstate_unmasked;
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}
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bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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{
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CPUClass *cc = CPU_GET_CLASS(cs);
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CPUClass *cc = CPU_GET_CLASS(cs);
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111
target/arm/cpu.h
111
target/arm/cpu.h
@ -2709,117 +2709,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
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#define ARM_CPUID_TI915T 0x54029152
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#define ARM_CPUID_TI915T 0x54029152
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#define ARM_CPUID_TI925T 0x54029252
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#define ARM_CPUID_TI925T 0x54029252
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static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
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unsigned int target_el)
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{
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CPUARMState *env = cs->env_ptr;
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unsigned int cur_el = arm_current_el(env);
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bool secure = arm_is_secure(env);
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bool pstate_unmasked;
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int8_t unmasked = 0;
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uint64_t hcr_el2;
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/* Don't take exceptions if they target a lower EL.
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* This check should catch any exceptions that would not be taken but left
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* pending.
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*/
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if (cur_el > target_el) {
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return false;
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}
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hcr_el2 = arm_hcr_el2_eff(env);
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switch (excp_idx) {
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case EXCP_FIQ:
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pstate_unmasked = !(env->daif & PSTATE_F);
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break;
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case EXCP_IRQ:
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pstate_unmasked = !(env->daif & PSTATE_I);
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break;
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case EXCP_VFIQ:
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if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
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/* VFIQs are only taken when hypervized and non-secure. */
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return false;
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}
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return !(env->daif & PSTATE_F);
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case EXCP_VIRQ:
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if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
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/* VIRQs are only taken when hypervized and non-secure. */
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return false;
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}
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return !(env->daif & PSTATE_I);
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default:
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g_assert_not_reached();
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}
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/* Use the target EL, current execution state and SCR/HCR settings to
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* determine whether the corresponding CPSR bit is used to mask the
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* interrupt.
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*/
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if ((target_el > cur_el) && (target_el != 1)) {
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/* Exceptions targeting a higher EL may not be maskable */
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if (arm_feature(env, ARM_FEATURE_AARCH64)) {
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/* 64-bit masking rules are simple: exceptions to EL3
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* can't be masked, and exceptions to EL2 can only be
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* masked from Secure state. The HCR and SCR settings
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* don't affect the masking logic, only the interrupt routing.
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*/
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if (target_el == 3 || !secure) {
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unmasked = 1;
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}
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} else {
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/* The old 32-bit-only environment has a more complicated
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* masking setup. HCR and SCR bits not only affect interrupt
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* routing but also change the behaviour of masking.
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*/
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bool hcr, scr;
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switch (excp_idx) {
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case EXCP_FIQ:
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/* If FIQs are routed to EL3 or EL2 then there are cases where
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* we override the CPSR.F in determining if the exception is
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* masked or not. If neither of these are set then we fall back
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* to the CPSR.F setting otherwise we further assess the state
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* below.
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*/
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hcr = hcr_el2 & HCR_FMO;
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scr = (env->cp15.scr_el3 & SCR_FIQ);
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/* When EL3 is 32-bit, the SCR.FW bit controls whether the
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* CPSR.F bit masks FIQ interrupts when taken in non-secure
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* state. If SCR.FW is set then FIQs can be masked by CPSR.F
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* when non-secure but only when FIQs are only routed to EL3.
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*/
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scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
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break;
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case EXCP_IRQ:
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/* When EL3 execution state is 32-bit, if HCR.IMO is set then
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* we may override the CPSR.I masking when in non-secure state.
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* The SCR.IRQ setting has already been taken into consideration
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* when setting the target EL, so it does not have a further
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* affect here.
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*/
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hcr = hcr_el2 & HCR_IMO;
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scr = false;
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break;
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default:
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g_assert_not_reached();
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}
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if ((scr || hcr) && !secure) {
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unmasked = 1;
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}
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}
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}
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/* The PSTATE bits only mask the interrupt if we have not overriden the
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* ability above.
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*/
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return unmasked || pstate_unmasked;
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}
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#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
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#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU
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#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
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#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX)
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#define CPU_RESOLVING_TYPE TYPE_ARM_CPU
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#define CPU_RESOLVING_TYPE TYPE_ARM_CPU
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