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tcg/loongarch64: Use 'z' constraint

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Replace target-specific 'Z' with generic 'z'.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-02-09 17:01:29 -08:00
parent 3d5939e57f
commit 305370e78d
3 changed files with 21 additions and 27 deletions
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15
tcg/loongarch64/tcg-target-con-set.h
View File

@ -15,8 +15,8 @@
* tcg-target-con-str.h; the constraint combination is inclusive or.
*/
C_O0_I1(r)
C_O0_I2(rZ, r)
C_O0_I2(rZ, rZ)
C_O0_I2(rz, r)
C_O0_I2(rz, rz)
C_O0_I2(w, r)
C_O0_I3(r, r, r)
C_O1_I1(r, r)
@ -28,14 +28,13 @@ C_O1_I2(r, r, rI)
C_O1_I2(r, r, rJ)
C_O1_I2(r, r, rU)
C_O1_I2(r, r, rW)
C_O1_I2(r, r, rZ)
C_O1_I2(r, 0, rZ)
C_O1_I2(r, rZ, ri)
C_O1_I2(r, rZ, rJ)
C_O1_I2(r, rZ, rZ)
C_O1_I2(r, 0, rz)
C_O1_I2(r, rz, ri)
C_O1_I2(r, rz, rJ)
C_O1_I2(r, rz, rz)
C_O1_I2(w, w, w)
C_O1_I2(w, w, wM)
C_O1_I2(w, w, wA)
C_O1_I3(w, w, w, w)
C_O1_I4(r, rZ, rJ, rZ, rZ)
C_O1_I4(r, rz, rJ, rz, rz)
C_N2_I1(r, r, r)

1
tcg/loongarch64/tcg-target-con-str.h
View File

@ -23,7 +23,6 @@ REGS('w', ALL_VECTOR_REGS)
CONST('I', TCG_CT_CONST_S12)
CONST('J', TCG_CT_CONST_S32)
CONST('U', TCG_CT_CONST_U12)
CONST('Z', TCG_CT_CONST_ZERO)
CONST('C', TCG_CT_CONST_C12)
CONST('W', TCG_CT_CONST_WSZ)
CONST('M', TCG_CT_CONST_VCMP)

32
tcg/loongarch64/tcg-target.c.inc
View File

@ -173,14 +173,13 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
#define TCG_GUEST_BASE_REG TCG_REG_S1
#define TCG_CT_CONST_ZERO 0x100
#define TCG_CT_CONST_S12 0x200
#define TCG_CT_CONST_S32 0x400
#define TCG_CT_CONST_U12 0x800
#define TCG_CT_CONST_C12 0x1000
#define TCG_CT_CONST_WSZ 0x2000
#define TCG_CT_CONST_VCMP 0x4000
#define TCG_CT_CONST_VADD 0x8000
#define TCG_CT_CONST_S12 0x100
#define TCG_CT_CONST_S32 0x200
#define TCG_CT_CONST_U12 0x400
#define TCG_CT_CONST_C12 0x800
#define TCG_CT_CONST_WSZ 0x1000
#define TCG_CT_CONST_VCMP 0x2000
#define TCG_CT_CONST_VADD 0x4000
#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32)
@ -197,9 +196,6 @@ static bool tcg_target_const_match(int64_t val, int ct,
if (ct & TCG_CT_CONST) {
return true;
}
if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
return true;
}
if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
return true;
}
@ -2229,7 +2225,7 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_st_i64:
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64:
return C_O0_I2(rZ, r);
return C_O0_I2(rz, r);
case INDEX_op_qemu_ld_i128:
return C_N2_I1(r, r, r);
@ -2239,7 +2235,7 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
return C_O0_I2(rZ, rZ);
return C_O0_I2(rz, rz);
case INDEX_op_ext8s_i32:
case INDEX_op_ext8s_i64:
@ -2332,14 +2328,14 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
/* Must deposit into the same register as input */
return C_O1_I2(r, 0, rZ);
return C_O1_I2(r, 0, rz);
case INDEX_op_sub_i32:
case INDEX_op_setcond_i32:
return C_O1_I2(r, rZ, ri);
return C_O1_I2(r, rz, ri);
case INDEX_op_sub_i64:
case INDEX_op_setcond_i64:
return C_O1_I2(r, rZ, rJ);
return C_O1_I2(r, rz, rJ);
case INDEX_op_mul_i32:
case INDEX_op_mul_i64:
@ -2355,11 +2351,11 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_rem_i64:
case INDEX_op_remu_i32:
case INDEX_op_remu_i64:
return C_O1_I2(r, rZ, rZ);
return C_O1_I2(r, rz, rz);
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
return C_O1_I4(r, rZ, rJ, rZ, rZ);
return C_O1_I4(r, rz, rJ, rz, rz);
case INDEX_op_ld_vec:
case INDEX_op_dupm_vec: