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target/riscv: Add Smdbltrp ISA extension enable switch

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Add the switch to enable the Smdbltrp ISA extension and disable it for
the max cpu. Indeed, OpenSBI when Smdbltrp is present, M-mode double
trap is enabled by default and MSTATUS.MDT needs to be cleared to avoid
taking a double trap. OpenSBI does not currently support it so disable
it for the max cpu to avoid breaking regression tests.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20250116131539.2475785-1-cleger@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Clément Léger 2025-01-16 14:15:36 +01:00 committed by Alistair Francis
parent 00af7d5360
commit 2d8e825928
2 changed files with 12 additions and 0 deletions
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2
target/riscv/cpu.c
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@ -194,6 +194,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_13_0, ext_smcdeleg), ISA_EXT_DATA_ENTRY(smcdeleg, PRIV_VERSION_1_13_0, ext_smcdeleg),
ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_13_0, ext_smcsrind), ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_13_0, ext_smcsrind),
ISA_EXT_DATA_ENTRY(smdbltrp, PRIV_VERSION_1_13_0, ext_smdbltrp),
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi),
ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm), ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_13_0, ext_smmpm),
@ -1626,6 +1627,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false), MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false),
MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false),
MULTI_EXT_CFG_BOOL("smdbltrp", ext_smdbltrp, false),
MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false),
MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false), MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false),

10
target/riscv/tcg/tcg-cpu.c
View File

@ -1439,6 +1439,16 @@ static void riscv_init_max_cpu_extensions(Object *obj)
isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false);
qemu_log("Smrnmi is disabled in the 'max' type CPU\n"); qemu_log("Smrnmi is disabled in the 'max' type CPU\n");
} }
/*
* ext_smdbltrp requires the firmware to clear MSTATUS.MDT on startup to
* avoid generating a double trap. OpenSBI does not currently support it,
* disable it for now.
*/
if (cpu->cfg.ext_smdbltrp) {
isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smdbltrp), false);
qemu_log("Smdbltrp is disabled in the 'max' type CPU\n");
}
} }
static bool riscv_cpu_has_max_extensions(Object *cpu_obj) static bool riscv_cpu_has_max_extensions(Object *cpu_obj)