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tests/qtest: Add intel-iommu test

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Add the framework to test the intel-iommu device.

Currently only tested cap/ecap bits correctness when x-flts=on in scalable
mode. Also tested cap/ecap bits consistency before and after system reset.

Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-21-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Zhenzhong Duan 2024-12-12 16:37:57 +08:00 committed by Michael S. Tsirkin
parent d9d32478ed
commit 2c746dfe1c
4 changed files with 67 additions and 0 deletions
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1
MAINTAINERS
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@ -3711,6 +3711,7 @@ F: hw/i386/intel_iommu.c
F: hw/i386/intel_iommu_internal.h
F: include/hw/i386/intel_iommu.h
F: tests/functional/test_intel_iommu.py
F: tests/qtest/intel-iommu-test.c
AMD-Vi Emulation
S: Orphan

1
include/hw/i386/intel_iommu.h
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@ -47,6 +47,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_DEVICE)
#define VTD_HOST_AW_48BIT 48
#define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_48BIT
#define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1)
#define VTD_MGAW_FROM_CAP(cap) ((cap >> 16) & 0x3fULL)
#define DMAR_REPORT_F_INTR (1)

64
tests/qtest/intel-iommu-test.c Normal file
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@ -0,0 +1,64 @@
/*
* QTest testcase for intel-iommu
*
* Copyright (c) 2024 Intel, Inc.
*
* Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "libqtest.h"
#include "hw/i386/intel_iommu_internal.h"
#define CAP_STAGE_1_FIXED1 (VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND | \
VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS)
#define ECAP_STAGE_1_FIXED1 (VTD_ECAP_QI | VTD_ECAP_IR | VTD_ECAP_IRO | \
VTD_ECAP_MHMV | VTD_ECAP_SMTS | VTD_ECAP_FLTS)
static inline uint64_t vtd_reg_readq(QTestState *s, uint64_t offset)
{
return qtest_readq(s, Q35_HOST_BRIDGE_IOMMU_ADDR + offset);
}
static void test_intel_iommu_stage_1(void)
{
uint8_t init_csr[DMAR_REG_SIZE]; /* register values */
uint8_t post_reset_csr[DMAR_REG_SIZE]; /* register values */
uint64_t cap, ecap, tmp;
QTestState *s;
s = qtest_init("-M q35 -device intel-iommu,x-scalable-mode=on,x-flts=on");
cap = vtd_reg_readq(s, DMAR_CAP_REG);
g_assert((cap & CAP_STAGE_1_FIXED1) == CAP_STAGE_1_FIXED1);
tmp = cap & VTD_CAP_SAGAW_MASK;
g_assert(tmp == (VTD_CAP_SAGAW_39bit | VTD_CAP_SAGAW_48bit));
tmp = VTD_MGAW_FROM_CAP(cap);
g_assert(tmp == VTD_HOST_AW_48BIT - 1);
ecap = vtd_reg_readq(s, DMAR_ECAP_REG);
g_assert((ecap & ECAP_STAGE_1_FIXED1) == ECAP_STAGE_1_FIXED1);
qtest_memread(s, Q35_HOST_BRIDGE_IOMMU_ADDR, init_csr, DMAR_REG_SIZE);
qobject_unref(qtest_qmp(s, "{ 'execute': 'system_reset' }"));
qtest_qmp_eventwait(s, "RESET");
qtest_memread(s, Q35_HOST_BRIDGE_IOMMU_ADDR, post_reset_csr, DMAR_REG_SIZE);
/* Ensure registers are consistent after hard reset */
g_assert(!memcmp(init_csr, post_reset_csr, DMAR_REG_SIZE));
qtest_quit(s);
}
int main(int argc, char **argv)
{
g_test_init(&argc, &argv, NULL);
qtest_add_func("/q35/intel-iommu/stage-1", test_intel_iommu_stage_1);
return g_test_run();
}

1
tests/qtest/meson.build
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@ -93,6 +93,7 @@ qtests_i386 = \
(config_all_devices.has_key('CONFIG_SB16') ? ['fuzz-sb16-test'] : []) + \
(config_all_devices.has_key('CONFIG_SDHCI_PCI') ? ['fuzz-sdcard-test'] : []) + \
(config_all_devices.has_key('CONFIG_ESP_PCI') ? ['am53c974-test'] : []) + \
(config_all_devices.has_key('CONFIG_VTD') ? ['intel-iommu-test'] : []) + \
(host_os != 'windows' and \
config_all_devices.has_key('CONFIG_ACPI_ERST') ? ['erst-test'] : []) + \
(config_all_devices.has_key('CONFIG_PCIE_PORT') and \