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target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32

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Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH
and HEDELEGH for exception codes 32-47 for reserving and exception codes
48-63 for custom use. Add the CSR number though the implementation is
just reading zero and writing ignore. Besides, for accessing HEDELEGH, it
should be controlled by mstateen0 'P1P13' bit.

Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240606135454.119186-5-fea.wang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Fea.Wang 2024-06-06 21:54:52 +08:00 committed by Alistair Francis
parent 7750e10656
commit 27796989ac
2 changed files with 33 additions and 0 deletions
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2
target/riscv/cpu_bits.h
View File

@ -156,6 +156,8 @@
/* 32-bit only */ /* 32-bit only */
#define CSR_MSTATUSH 0x310 #define CSR_MSTATUSH 0x310
#define CSR_MEDELEGH 0x312
#define CSR_HEDELEGH 0x612
/* Machine Trap Handling */ /* Machine Trap Handling */
#define CSR_MSCRATCH 0x340 #define CSR_MSCRATCH 0x340

31
target/riscv/csr.c
View File

@ -3229,6 +3229,33 @@ static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
static RISCVException read_hedelegh(CPURISCVState *env, int csrno,
target_ulong *val)
{
RISCVException ret;
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13);
if (ret != RISCV_EXCP_NONE) {
return ret;
}
/* Reserved, now read zero */
*val = 0;
return RISCV_EXCP_NONE;
}
static RISCVException write_hedelegh(CPURISCVState *env, int csrno,
target_ulong val)
{
RISCVException ret;
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_P1P13);
if (ret != RISCV_EXCP_NONE) {
return ret;
}
/* Reserved, now write ignore */
return RISCV_EXCP_NONE;
}
static RISCVException rmw_hvien64(CPURISCVState *env, int csrno, static RISCVException rmw_hvien64(CPURISCVState *env, int csrno,
uint64_t *ret_val, uint64_t *ret_val,
uint64_t new_val, uint64_t wr_mask) uint64_t new_val, uint64_t wr_mask)
@ -4633,6 +4660,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush,
write_mstatush }, write_mstatush },
[CSR_MEDELEGH] = { "medelegh", any32, read_zero, write_ignore,
.min_priv_ver = PRIV_VERSION_1_13_0 },
[CSR_HEDELEGH] = { "hedelegh", hmode32, read_hedelegh, write_hedelegh,
.min_priv_ver = PRIV_VERSION_1_13_0 },
/* Machine Trap Handling */ /* Machine Trap Handling */
[CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch, [CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch,