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hw/block/nvme: alignment style fixes

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Style fixes.

Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
This commit is contained in:
Klaus Jensen 2020-08-24 08:58:56 +02:00
parent c6056bd1ce
commit 2750384669
1 changed files with 13 additions and 12 deletions
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25
hw/block/nvme.c
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@ -634,7 +634,7 @@ static void nvme_rw_cb(void *opaque, int ret)
static uint16_t nvme_flush(NvmeCtrl *n, NvmeRequest *req) static uint16_t nvme_flush(NvmeCtrl *n, NvmeRequest *req)
{ {
block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0, block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
BLOCK_ACCT_FLUSH); BLOCK_ACCT_FLUSH);
req->aiocb = blk_aio_flush(n->conf.blk, nvme_rw_cb, req); req->aiocb = blk_aio_flush(n->conf.blk, nvme_rw_cb, req);
return NVME_NO_COMPLETE; return NVME_NO_COMPLETE;
@ -663,7 +663,7 @@ static uint16_t nvme_write_zeroes(NvmeCtrl *n, NvmeRequest *req)
block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0, block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
BLOCK_ACCT_WRITE); BLOCK_ACCT_WRITE);
req->aiocb = blk_aio_pwrite_zeroes(n->conf.blk, offset, count, req->aiocb = blk_aio_pwrite_zeroes(n->conf.blk, offset, count,
BDRV_REQ_MAY_UNMAP, nvme_rw_cb, req); BDRV_REQ_MAY_UNMAP, nvme_rw_cb, req);
return NVME_NO_COMPLETE; return NVME_NO_COMPLETE;
} }
@ -803,7 +803,7 @@ static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeRequest *req)
} }
static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr, static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,
uint16_t sqid, uint16_t cqid, uint16_t size) uint16_t sqid, uint16_t cqid, uint16_t size)
{ {
int i; int i;
NvmeCQueue *cq; NvmeCQueue *cq;
@ -1058,7 +1058,8 @@ static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeRequest *req)
} }
static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr, static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr,
uint16_t cqid, uint16_t vector, uint16_t size, uint16_t irq_enabled) uint16_t cqid, uint16_t vector, uint16_t size,
uint16_t irq_enabled)
{ {
int ret; int ret;
@ -1118,7 +1119,7 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeRequest *req)
cq = g_malloc0(sizeof(*cq)); cq = g_malloc0(sizeof(*cq));
nvme_init_cq(cq, n, prp1, cqid, vector, qsize + 1, nvme_init_cq(cq, n, prp1, cqid, vector, qsize + 1,
NVME_CQ_FLAGS_IEN(qflags)); NVME_CQ_FLAGS_IEN(qflags));
/* /*
* It is only required to set qs_created when creating a completion queue; * It is only required to set qs_created when creating a completion queue;
@ -1515,7 +1516,7 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRequest *req)
} }
if (((n->temperature >= n->features.temp_thresh_hi) || if (((n->temperature >= n->features.temp_thresh_hi) ||
(n->temperature <= n->features.temp_thresh_low)) && (n->temperature <= n->features.temp_thresh_low)) &&
NVME_AEC_SMART(n->features.async_config) & NVME_SMART_TEMPERATURE) { NVME_AEC_SMART(n->features.async_config) & NVME_SMART_TEMPERATURE) {
nvme_enqueue_event(n, NVME_AER_TYPE_SMART, nvme_enqueue_event(n, NVME_AER_TYPE_SMART,
NVME_AER_INFO_SMART_TEMP_THRESH, NVME_AER_INFO_SMART_TEMP_THRESH,
@ -1765,9 +1766,9 @@ static int nvme_start_ctrl(NvmeCtrl *n)
n->cqe_size = 1 << NVME_CC_IOCQES(n->bar.cc); n->cqe_size = 1 << NVME_CC_IOCQES(n->bar.cc);
n->sqe_size = 1 << NVME_CC_IOSQES(n->bar.cc); n->sqe_size = 1 << NVME_CC_IOSQES(n->bar.cc);
nvme_init_cq(&n->admin_cq, n, n->bar.acq, 0, 0, nvme_init_cq(&n->admin_cq, n, n->bar.acq, 0, 0,
NVME_AQA_ACQS(n->bar.aqa) + 1, 1); NVME_AQA_ACQS(n->bar.aqa) + 1, 1);
nvme_init_sq(&n->admin_sq, n, n->bar.asq, 0, 0, nvme_init_sq(&n->admin_sq, n, n->bar.asq, 0, 0,
NVME_AQA_ASQS(n->bar.aqa) + 1); NVME_AQA_ASQS(n->bar.aqa) + 1);
nvme_set_timestamp(n, 0ULL); nvme_set_timestamp(n, 0ULL);
@ -1777,7 +1778,7 @@ static int nvme_start_ctrl(NvmeCtrl *n)
} }
static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data, static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
unsigned size) unsigned size)
{ {
if (unlikely(offset & (sizeof(uint32_t) - 1))) { if (unlikely(offset & (sizeof(uint32_t) - 1))) {
NVME_GUEST_ERR(pci_nvme_ub_mmiowr_misaligned32, NVME_GUEST_ERR(pci_nvme_ub_mmiowr_misaligned32,
@ -1920,7 +1921,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
"invalid write to PMRSWTP register, ignored"); "invalid write to PMRSWTP register, ignored");
return; return;
case 0xE14: /* TODO PMRMSC */ case 0xE14: /* TODO PMRMSC */
break; break;
default: default:
NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid, NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid,
"invalid MMIO write," "invalid MMIO write,"
@ -2096,7 +2097,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
} }
static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data, static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data,
unsigned size) unsigned size)
{ {
NvmeCtrl *n = (NvmeCtrl *)opaque; NvmeCtrl *n = (NvmeCtrl *)opaque;
@ -2120,7 +2121,7 @@ static const MemoryRegionOps nvme_mmio_ops = {
}; };
static void nvme_cmb_write(void *opaque, hwaddr addr, uint64_t data, static void nvme_cmb_write(void *opaque, hwaddr addr, uint64_t data,
unsigned size) unsigned size)
{ {
NvmeCtrl *n = (NvmeCtrl *)opaque; NvmeCtrl *n = (NvmeCtrl *)opaque;
stn_le_p(&n->cmbuf[addr], size, data); stn_le_p(&n->cmbuf[addr], size, data);