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target/arm: Fix ATS12NSO* from S PL1

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Use arm_hcr_el2_eff_secstate instead of arm_hcr_el2_eff, so
that we use is_secure instead of the current security state.
These AT* operations have been broken since arm_hcr_el2_eff
gained a check for "el2 enabled" for Secure EL2.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-10-01 09:22:53 -07:00 committed by Peter Maydell
parent ac76c2e508
commit 2189c79858
1 changed files with 4 additions and 4 deletions
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8
target/arm/ptw.c
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@ -146,7 +146,7 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
} }
} }
hcr_el2 = arm_hcr_el2_eff(env); hcr_el2 = arm_hcr_el2_eff_secstate(env, is_secure);
switch (mmu_idx) { switch (mmu_idx) {
case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2:
@ -230,7 +230,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
return ~0; return ~0;
} }
hcr = arm_hcr_el2_eff(env); hcr = arm_hcr_el2_eff_secstate(env, is_secure);
if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) { if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) {
/* /*
* PTW set and S1 walk touched S2 Device memory: * PTW set and S1 walk touched S2 Device memory:
@ -2341,7 +2341,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
} }
/* Combine the S1 and S2 cache attributes. */ /* Combine the S1 and S2 cache attributes. */
hcr = arm_hcr_el2_eff(env); hcr = arm_hcr_el2_eff_secstate(env, is_secure);
if (hcr & HCR_DC) { if (hcr & HCR_DC) {
/* /*
* HCR.DC forces the first stage attributes to * HCR.DC forces the first stage attributes to
@ -2473,7 +2473,7 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
result->page_size = TARGET_PAGE_SIZE; result->page_size = TARGET_PAGE_SIZE;
/* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
hcr = arm_hcr_el2_eff(env); hcr = arm_hcr_el2_eff_secstate(env, is_secure);
result->cacheattrs.shareability = 0; result->cacheattrs.shareability = 0;
result->cacheattrs.is_s2_format = false; result->cacheattrs.is_s2_format = false;
if (hcr & HCR_DC) { if (hcr & HCR_DC) {