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target/cris: Convert to 3-phase reset

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Convert the cris CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Message-id: 20221124115023.2437291-5-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-11-24 11:50:07 +00:00
parent 605787606e
commit 1d2eb1c0c5
2 changed files with 10 additions and 6 deletions
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4
target/cris/cpu-qom.h
View File

@ -30,7 +30,7 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
/** /**
* CRISCPUClass: * CRISCPUClass:
* @parent_realize: The parent class' realize handler. * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler. * @parent_phases: The parent class' reset phase handlers.
* @vr: Version Register value. * @vr: Version Register value.
* *
* A CRIS CPU model. * A CRIS CPU model.
@ -41,7 +41,7 @@ struct CRISCPUClass {
/*< public >*/ /*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
DeviceReset parent_reset; ResettablePhases parent_phases;
uint32_t vr; uint32_t vr;
}; };

12
target/cris/cpu.c
View File

@ -56,15 +56,17 @@ static bool cris_cpu_has_work(CPUState *cs)
return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
} }
static void cris_cpu_reset(DeviceState *dev) static void cris_cpu_reset_hold(Object *obj)
{ {
CPUState *s = CPU(dev); CPUState *s = CPU(obj);
CRISCPU *cpu = CRIS_CPU(s); CRISCPU *cpu = CRIS_CPU(s);
CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu);
CPUCRISState *env = &cpu->env; CPUCRISState *env = &cpu->env;
uint32_t vr; uint32_t vr;
ccc->parent_reset(dev); if (ccc->parent_phases.hold) {
ccc->parent_phases.hold(obj);
}
vr = env->pregs[PR_VR]; vr = env->pregs[PR_VR];
memset(env, 0, offsetof(CPUCRISState, end_reset_fields)); memset(env, 0, offsetof(CPUCRISState, end_reset_fields));
@ -305,11 +307,13 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, cris_cpu_realizefn, device_class_set_parent_realize(dc, cris_cpu_realizefn,
&ccc->parent_realize); &ccc->parent_realize);
device_class_set_parent_reset(dc, cris_cpu_reset, &ccc->parent_reset); resettable_class_set_parent_phases(rc, NULL, cris_cpu_reset_hold, NULL,
&ccc->parent_phases);
cc->class_by_name = cris_cpu_class_by_name; cc->class_by_name = cris_cpu_class_by_name;
cc->has_work = cris_cpu_has_work; cc->has_work = cris_cpu_has_work;