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tcg/sparc64: Use 'z' constraint

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Replace target-specific 'Z' with generic 'z'.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-02-09 18:11:20 -08:00
parent f466db1e27
commit 1bbcae5ada
3 changed files with 13 additions and 17 deletions
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12
tcg/sparc64/tcg-target-con-set.h
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@ -10,11 +10,11 @@
* tcg-target-con-str.h; the constraint combination is inclusive or. * tcg-target-con-str.h; the constraint combination is inclusive or.
*/ */
C_O0_I1(r) C_O0_I1(r)
C_O0_I2(rZ, r) C_O0_I2(rz, r)
C_O0_I2(rZ, rJ) C_O0_I2(rz, rJ)
C_O1_I1(r, r) C_O1_I1(r, r)
C_O1_I2(r, r, r) C_O1_I2(r, r, r)
C_O1_I2(r, rZ, rJ) C_O1_I2(r, rz, rJ)
C_O1_I4(r, rZ, rJ, rI, 0) C_O1_I4(r, rz, rJ, rI, 0)
C_O2_I2(r, r, rZ, rJ) C_O2_I2(r, r, rz, rJ)
C_O2_I4(r, r, rZ, rZ, rJ, rJ) C_O2_I4(r, r, rz, rz, rJ, rJ)

1
tcg/sparc64/tcg-target-con-str.h
View File

@ -16,4 +16,3 @@ REGS('r', ALL_GENERAL_REGS)
*/ */
CONST('I', TCG_CT_CONST_S11) CONST('I', TCG_CT_CONST_S11)
CONST('J', TCG_CT_CONST_S13) CONST('J', TCG_CT_CONST_S13)
CONST('Z', TCG_CT_CONST_ZERO)

17
tcg/sparc64/tcg-target.c.inc
View File

@ -76,7 +76,6 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
#define TCG_CT_CONST_S11 0x100 #define TCG_CT_CONST_S11 0x100
#define TCG_CT_CONST_S13 0x200 #define TCG_CT_CONST_S13 0x200
#define TCG_CT_CONST_ZERO 0x400
#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
@ -340,9 +339,7 @@ static bool tcg_target_const_match(int64_t val, int ct,
val = (int32_t)val; val = (int32_t)val;
} }
if ((ct & TCG_CT_CONST_ZERO) && val == 0) { if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) {
return 1;
} else if ((ct & TCG_CT_CONST_S11) && check_fit_tl(val, 11)) {
return 1; return 1;
} else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) { } else if ((ct & TCG_CT_CONST_S13) && check_fit_tl(val, 13)) {
return 1; return 1;
@ -1579,7 +1576,7 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_st_i64: case INDEX_op_st_i64:
case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64: case INDEX_op_qemu_st_i64:
return C_O0_I2(rZ, r); return C_O0_I2(rz, r);
case INDEX_op_add_i32: case INDEX_op_add_i32:
case INDEX_op_add_i64: case INDEX_op_add_i64:
@ -1611,22 +1608,22 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_setcond_i64: case INDEX_op_setcond_i64:
case INDEX_op_negsetcond_i32: case INDEX_op_negsetcond_i32:
case INDEX_op_negsetcond_i64: case INDEX_op_negsetcond_i64:
return C_O1_I2(r, rZ, rJ); return C_O1_I2(r, rz, rJ);
case INDEX_op_brcond_i32: case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64: case INDEX_op_brcond_i64:
return C_O0_I2(rZ, rJ); return C_O0_I2(rz, rJ);
case INDEX_op_movcond_i32: case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64: case INDEX_op_movcond_i64:
return C_O1_I4(r, rZ, rJ, rI, 0); return C_O1_I4(r, rz, rJ, rI, 0);
case INDEX_op_add2_i32: case INDEX_op_add2_i32:
case INDEX_op_add2_i64: case INDEX_op_add2_i64:
case INDEX_op_sub2_i32: case INDEX_op_sub2_i32:
case INDEX_op_sub2_i64: case INDEX_op_sub2_i64:
return C_O2_I4(r, r, rZ, rZ, rJ, rJ); return C_O2_I4(r, r, rz, rz, rJ, rJ);
case INDEX_op_mulu2_i32: case INDEX_op_mulu2_i32:
case INDEX_op_muls2_i32: case INDEX_op_muls2_i32:
return C_O2_I2(r, r, rZ, rJ); return C_O2_I2(r, r, rz, rJ);
case INDEX_op_muluh_i64: case INDEX_op_muluh_i64:
return C_O1_I2(r, r, r); return C_O1_I2(r, r, r);