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target/mips: Extract decode_64bit_enabled() helper

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Extract the decode_64bit_enabled() helper which detects
whether CPUs can run 64-bit instructions.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20241026175349.84523-2-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2024-10-26 14:15:26 -03:00
parent 5d3d52229b
commit 1b63c0b7a5
2 changed files with 8 additions and 1 deletions
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7
target/mips/tcg/translate.c
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@ -1645,13 +1645,18 @@ static inline void check_ps(DisasContext *ctx)
check_cp1_64bitmode(ctx); check_cp1_64bitmode(ctx);
} }
bool decode_64bit_enabled(DisasContext *ctx)
{
return ctx->hflags & MIPS_HFLAG_64;
}
/* /*
* This code generates a "reserved instruction" exception if cpu is not * This code generates a "reserved instruction" exception if cpu is not
* 64-bit or 64-bit instructions are not enabled. * 64-bit or 64-bit instructions are not enabled.
*/ */
void check_mips_64(DisasContext *ctx) void check_mips_64(DisasContext *ctx)
{ {
if (unlikely((TARGET_LONG_BITS != 64) || !(ctx->hflags & MIPS_HFLAG_64))) { if (unlikely((TARGET_LONG_BITS != 64) || !decode_64bit_enabled(ctx))) {
gen_reserved_instruction(ctx); gen_reserved_instruction(ctx);
} }
} }

2
target/mips/tcg/translate.h
View File

@ -217,6 +217,8 @@ void msa_translate_init(void);
void mxu_translate_init(void); void mxu_translate_init(void);
bool decode_ase_mxu(DisasContext *ctx, uint32_t insn); bool decode_ase_mxu(DisasContext *ctx, uint32_t insn);
bool decode_64bit_enabled(DisasContext *ctx);
/* decodetree generated */ /* decodetree generated */
bool decode_isa_rel6(DisasContext *ctx, uint32_t insn); bool decode_isa_rel6(DisasContext *ctx, uint32_t insn);
bool decode_ase_msa(DisasContext *ctx, uint32_t insn); bool decode_ase_msa(DisasContext *ctx, uint32_t insn);