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target/arm: Plumb FEAT_RPRES frecpe and frsqrte through to new helper

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FEAT_RPRES implements an "increased precision" variant of the single
precision FRECPE and FRSQRTE instructions from an 8 bit to a 12
bit mantissa. This applies only when FPCR.AH == 1. Note that the
halfprec and double versions of these insns retain the 8 bit
precision regardless.

In this commit we add all the plumbing to make these instructions
call a new helper function when the increased-precision is in
effect. In the following commit we will provide the actual change
in behaviour in the helpers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell 2025-02-01 16:39:56 +00:00
parent d38a57a3f1
commit 0ff5c021f0
6 changed files with 85 additions and 8 deletions
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5
target/arm/cpu-features.h
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@ -597,6 +597,11 @@ static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS);
}
static inline bool isar_feature_aa64_rpres(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, RPRES);
}
static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
{
/* We always set the AdvSIMD and FP fields identically. */

4
target/arm/helper.h
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@ -245,9 +245,11 @@ DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, fpst)
DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
DEF_HELPER_FLAGS_2(recpe_rpres_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, fpst)
DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
DEF_HELPER_FLAGS_2(rsqrte_rpres_f32, TCG_CALL_NO_RWG, f32, f32, fpst)
DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, fpst)
DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)
DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)
@ -680,10 +682,12 @@ DEF_HELPER_FLAGS_4(gvec_vrintx_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_frecpe_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_frecpe_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_frecpe_rpres_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_frecpe_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_frsqrte_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_frsqrte_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_frsqrte_rpres_s, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_frsqrte_d, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)
DEF_HELPER_FLAGS_4(gvec_fcgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, fpst, i32)

34
target/arm/tcg/translate-a64.c
View File

@ -8903,7 +8903,14 @@ static const FPScalar1 f_scalar_frecpe = {
gen_helper_recpe_f32,
gen_helper_recpe_f64,
};
TRANS(FRECPE_s, do_fp1_scalar_ah, a, &f_scalar_frecpe, -1)
static const FPScalar1 f_scalar_frecpe_rpres = {
gen_helper_recpe_f16,
gen_helper_recpe_rpres_f32,
gen_helper_recpe_f64,
};
TRANS(FRECPE_s, do_fp1_scalar_ah, a,
s->fpcr_ah && dc_isar_feature(aa64_rpres, s) ?
&f_scalar_frecpe_rpres : &f_scalar_frecpe, -1)
static const FPScalar1 f_scalar_frecpx = {
gen_helper_frecpx_f16,
@ -8917,7 +8924,14 @@ static const FPScalar1 f_scalar_frsqrte = {
gen_helper_rsqrte_f32,
gen_helper_rsqrte_f64,
};
TRANS(FRSQRTE_s, do_fp1_scalar_ah, a, &f_scalar_frsqrte, -1)
static const FPScalar1 f_scalar_frsqrte_rpres = {
gen_helper_rsqrte_f16,
gen_helper_rsqrte_rpres_f32,
gen_helper_rsqrte_f64,
};
TRANS(FRSQRTE_s, do_fp1_scalar_ah, a,
s->fpcr_ah && dc_isar_feature(aa64_rpres, s) ?
&f_scalar_frsqrte_rpres : &f_scalar_frsqrte, -1)
static bool trans_FCVT_s_ds(DisasContext *s, arg_rr *a)
{
@ -9948,14 +9962,26 @@ static gen_helper_gvec_2_ptr * const f_frecpe[] = {
gen_helper_gvec_frecpe_s,
gen_helper_gvec_frecpe_d,
};
TRANS(FRECPE_v, do_gvec_op2_ah_fpst, a->esz, a->q, a->rd, a->rn, 0, f_frecpe)
static gen_helper_gvec_2_ptr * const f_frecpe_rpres[] = {
gen_helper_gvec_frecpe_h,
gen_helper_gvec_frecpe_rpres_s,
gen_helper_gvec_frecpe_d,
};
TRANS(FRECPE_v, do_gvec_op2_ah_fpst, a->esz, a->q, a->rd, a->rn, 0,
s->fpcr_ah && dc_isar_feature(aa64_rpres, s) ? f_frecpe_rpres : f_frecpe)
static gen_helper_gvec_2_ptr * const f_frsqrte[] = {
gen_helper_gvec_frsqrte_h,
gen_helper_gvec_frsqrte_s,
gen_helper_gvec_frsqrte_d,
};
TRANS(FRSQRTE_v, do_gvec_op2_ah_fpst, a->esz, a->q, a->rd, a->rn, 0, f_frsqrte)
static gen_helper_gvec_2_ptr * const f_frsqrte_rpres[] = {
gen_helper_gvec_frsqrte_h,
gen_helper_gvec_frsqrte_rpres_s,
gen_helper_gvec_frsqrte_d,
};
TRANS(FRSQRTE_v, do_gvec_op2_ah_fpst, a->esz, a->q, a->rd, a->rn, 0,
s->fpcr_ah && dc_isar_feature(aa64_rpres, s) ? f_frsqrte_rpres : f_frsqrte)
static bool trans_FCVTL_v(DisasContext *s, arg_qrr_e *a)
{

16
target/arm/tcg/translate-sve.c
View File

@ -3629,13 +3629,25 @@ static gen_helper_gvec_2_ptr * const frecpe_fns[] = {
NULL, gen_helper_gvec_frecpe_h,
gen_helper_gvec_frecpe_s, gen_helper_gvec_frecpe_d,
};
TRANS_FEAT(FRECPE, aa64_sve, gen_gvec_fpst_ah_arg_zz, frecpe_fns[a->esz], a, 0)
static gen_helper_gvec_2_ptr * const frecpe_rpres_fns[] = {
NULL, gen_helper_gvec_frecpe_h,
gen_helper_gvec_frecpe_rpres_s, gen_helper_gvec_frecpe_d,
};
TRANS_FEAT(FRECPE, aa64_sve, gen_gvec_fpst_ah_arg_zz,
s->fpcr_ah && dc_isar_feature(aa64_rpres, s) ?
frecpe_rpres_fns[a->esz] : frecpe_fns[a->esz], a, 0)
static gen_helper_gvec_2_ptr * const frsqrte_fns[] = {
NULL, gen_helper_gvec_frsqrte_h,
gen_helper_gvec_frsqrte_s, gen_helper_gvec_frsqrte_d,
};
TRANS_FEAT(FRSQRTE, aa64_sve, gen_gvec_fpst_ah_arg_zz, frsqrte_fns[a->esz], a, 0)
static gen_helper_gvec_2_ptr * const frsqrte_rpres_fns[] = {
NULL, gen_helper_gvec_frsqrte_h,
gen_helper_gvec_frsqrte_rpres_s, gen_helper_gvec_frsqrte_d,
};
TRANS_FEAT(FRSQRTE, aa64_sve, gen_gvec_fpst_ah_arg_zz,
s->fpcr_ah && dc_isar_feature(aa64_rpres, s) ?
frsqrte_rpres_fns[a->esz] : frsqrte_fns[a->esz], a, 0)
/*
*** SVE Floating Point Compare with Zero Group

2
target/arm/tcg/vec_helper.c
View File

@ -1236,10 +1236,12 @@ void HELPER(NAME)(void *vd, void *vn, float_status *stat, uint32_t desc) \
DO_2OP(gvec_frecpe_h, helper_recpe_f16, float16)
DO_2OP(gvec_frecpe_s, helper_recpe_f32, float32)
DO_2OP(gvec_frecpe_rpres_s, helper_recpe_rpres_f32, float32)
DO_2OP(gvec_frecpe_d, helper_recpe_f64, float64)
DO_2OP(gvec_frsqrte_h, helper_rsqrte_f16, float16)
DO_2OP(gvec_frsqrte_s, helper_rsqrte_f32, float32)
DO_2OP(gvec_frsqrte_rpres_s, helper_rsqrte_rpres_f32, float32)
DO_2OP(gvec_frsqrte_d, helper_rsqrte_f64, float64)
DO_2OP(gvec_vrintx_h, float16_round_to_int, float16)

32
target/arm/vfp_helper.c
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@ -841,7 +841,11 @@ uint32_t HELPER(recpe_f16)(uint32_t input, float_status *fpst)
return make_float16(f16_val);
}
float32 HELPER(recpe_f32)(float32 input, float_status *fpst)
/*
* FEAT_RPRES means the f32 FRECPE has an "increased precision" variant
* which is used when FPCR.AH == 1.
*/
static float32 do_recpe_f32(float32 input, float_status *fpst, bool rpres)
{
float32 f32 = float32_squash_input_denormal(input, fpst);
uint32_t f32_val = float32_val(f32);
@ -890,6 +894,16 @@ float32 HELPER(recpe_f32)(float32 input, float_status *fpst)
return make_float32(f32_val);
}
float32 HELPER(recpe_f32)(float32 input, float_status *fpst)
{
return do_recpe_f32(input, fpst, false);
}
float32 HELPER(recpe_rpres_f32)(float32 input, float_status *fpst)
{
return do_recpe_f32(input, fpst, true);
}
float64 HELPER(recpe_f64)(float64 input, float_status *fpst)
{
float64 f64 = float64_squash_input_denormal(input, fpst);
@ -1035,7 +1049,11 @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, float_status *s)
return make_float16(val);
}
float32 HELPER(rsqrte_f32)(float32 input, float_status *s)
/*
* FEAT_RPRES means the f32 FRSQRTE has an "increased precision" variant
* which is used when FPCR.AH == 1.
*/
static float32 do_rsqrte_f32(float32 input, float_status *s, bool rpres)
{
float32 f32 = float32_squash_input_denormal(input, s);
uint32_t val = float32_val(f32);
@ -1080,6 +1098,16 @@ float32 HELPER(rsqrte_f32)(float32 input, float_status *s)
return make_float32(val);
}
float32 HELPER(rsqrte_f32)(float32 input, float_status *s)
{
return do_rsqrte_f32(input, s, false);
}
float32 HELPER(rsqrte_rpres_f32)(float32 input, float_status *s)
{
return do_rsqrte_f32(input, s, true);
}
float64 HELPER(rsqrte_f64)(float64 input, float_status *s)
{
float64 f64 = float64_squash_input_denormal(input, s);