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Fifth RISC-V PR for 10.0

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* Add docs/specs/riscv-iommu.rst to MAINTAINERS
 * Fix broken link to external risv iommu document
 * Revert scounteren and senvcfg to fixup older kernel boots
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Merge tag 'pull-riscv-to-apply-20250328' of https://github.com/alistair23/qemu into staging

Fifth RISC-V PR for 10.0

* Add docs/specs/riscv-iommu.rst to MAINTAINERS
* Fix broken link to external risv iommu document
* Revert scounteren and senvcfg to fixup older kernel boots

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* tag 'pull-riscv-to-apply-20250328' of https://github.com/alistair23/qemu:
  Revert "target/riscv/kvm: add missing KVM CSRs"
  docs/specs/riscv-iommu: Fixed broken link to external risv iommu document
  docs: Added docs/specs/riscv-iommu.rst in MAINTAINERS file.

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2025-03-28 08:06:53 -04:00
commit 0f15892aca
3 changed files with 4 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -319,6 +319,7 @@ L: qemu-riscv@nongnu.org
S: Supported
F: configs/targets/riscv*
F: docs/system/target-riscv.rst
F: docs/specs/riscv-iommu.rst
F: target/riscv/
F: hw/char/riscv_htif.c
F: hw/riscv/

6
docs/specs/riscv-iommu.rst
View File

@ -4,7 +4,7 @@ RISC-V IOMMU support for RISC-V machines
========================================
QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec
version 1.0 `iommu1.0`_.
version 1.0 `iommu1.0.0`_.
The emulation includes a PCI reference device (riscv-iommu-pci) and a platform
bus device (riscv-iommu-sys) that QEMU RISC-V boards can use. The 'virt'
@ -14,7 +14,7 @@ riscv-iommu-pci reference device
--------------------------------
This device implements the RISC-V IOMMU emulation as recommended by the section
"Integrating an IOMMU as a PCIe device" of `iommu1.0`_: a PCI device with base
"Integrating an IOMMU as a PCIe device" of `iommu1.0.0`_: a PCI device with base
class 08h, sub-class 06h and programming interface 00h.
As a reference device it doesn't implement anything outside of the specification,
@ -109,7 +109,7 @@ riscv-iommu options:
- "s-stage": enabled
- "g-stage": enabled
.. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf
.. _iommu1.0.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0.0/riscv-iommu.pdf
.. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tjeznach@rivosinc.com/

6
target/riscv/kvm/kvm-cpu.c
View File

@ -624,8 +624,6 @@ static void kvm_riscv_reset_regs_csr(CPURISCVState *env)
env->stval = 0;
env->mip = 0;
env->satp = 0;
env->scounteren = 0;
env->senvcfg = 0;
}
static int kvm_riscv_get_regs_csr(CPUState *cs)
@ -641,8 +639,6 @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
KVM_RISCV_GET_CSR(cs, env, stval, env->stval);
KVM_RISCV_GET_CSR(cs, env, sip, env->mip);
KVM_RISCV_GET_CSR(cs, env, satp, env->satp);
KVM_RISCV_GET_CSR(cs, env, scounteren, env->scounteren);
KVM_RISCV_GET_CSR(cs, env, senvcfg, env->senvcfg);
return 0;
}
@ -660,8 +656,6 @@ static int kvm_riscv_put_regs_csr(CPUState *cs)
KVM_RISCV_SET_CSR(cs, env, stval, env->stval);
KVM_RISCV_SET_CSR(cs, env, sip, env->mip);
KVM_RISCV_SET_CSR(cs, env, satp, env->satp);
KVM_RISCV_SET_CSR(cs, env, scounteren, env->scounteren);
KVM_RISCV_SET_CSR(cs, env, senvcfg, env->senvcfg);
return 0;
}