SYS-OSS/FRET-qemu
4
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

tcg/mips: Drop addrhi from prepare_host_addr

Browse Source 
The guest address will now always fit in one register.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-02-04 17:43:23 -08:00
parent dc8e2f8f78
commit 0d000618d9
1 changed files with 22 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

62
tcg/mips/tcg-target.c.inc
View File

@ -1217,8 +1217,7 @@ bool tcg_target_has_memory_bswap(MemOp memop)
* is required and fill in @h with the host address for the fast path. * is required and fill in @h with the host address for the fast path.
*/ */
static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
TCGReg addrlo, TCGReg addrhi, TCGReg addr, MemOpIdx oi, bool is_ld)
MemOpIdx oi, bool is_ld)
{ {
TCGType addr_type = s->addr_type; TCGType addr_type = s->addr_type;
TCGLabelQemuLdst *ldst = NULL; TCGLabelQemuLdst *ldst = NULL;
@ -1245,8 +1244,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addrlo; ldst->addrlo_reg = addr;
ldst->addrhi_reg = addrhi;
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
@ -1254,11 +1252,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
/* Extract the TLB index from the address into TMP3. */ /* Extract the TLB index from the address into TMP3. */
if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo, tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr,
s->page_bits - CPU_TLB_ENTRY_BITS); s->page_bits - CPU_TLB_ENTRY_BITS);
} else { } else {
tcg_out_dsrl(s, TCG_TMP3, addrlo, tcg_out_dsrl(s, TCG_TMP3, addr, s->page_bits - CPU_TLB_ENTRY_BITS);
s->page_bits - CPU_TLB_ENTRY_BITS);
} }
tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
@ -1288,48 +1285,35 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32 tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32
|| addr_type == TCG_TYPE_I32 || addr_type == TCG_TYPE_I32
? OPC_ADDIU : OPC_DADDIU), ? OPC_ADDIU : OPC_DADDIU),
TCG_TMP2, addrlo, s_mask - a_mask); TCG_TMP2, addr, s_mask - a_mask);
tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
} else { } else {
tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addr);
} }
/* Zero extend a 32-bit guest address for a 64-bit host. */ /* Zero extend a 32-bit guest address for a 64-bit host. */
if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
tcg_out_ext32u(s, TCG_TMP2, addrlo); tcg_out_ext32u(s, TCG_TMP2, addr);
addrlo = TCG_TMP2; addr = TCG_TMP2;
} }
ldst->label_ptr[0] = s->code_ptr; ldst->label_ptr[0] = s->code_ptr;
tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
/* Load and test the high half tlb comparator. */
if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) {
/* delay slot */
tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
/* Load the tlb addend for the fast path. */
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
ldst->label_ptr[1] = s->code_ptr;
tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0);
}
/* delay slot */ /* delay slot */
base = TCG_TMP3; base = TCG_TMP3;
tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo); tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr);
} else { } else {
if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) {
ldst = new_ldst_label(s); ldst = new_ldst_label(s);
ldst->is_ld = is_ld; ldst->is_ld = is_ld;
ldst->oi = oi; ldst->oi = oi;
ldst->addrlo_reg = addrlo; ldst->addrlo_reg = addr;
ldst->addrhi_reg = addrhi;
/* We are expecting a_bits to max out at 7, much lower than ANDI. */ /* We are expecting a_bits to max out at 7, much lower than ANDI. */
tcg_debug_assert(a_bits < 16); tcg_debug_assert(a_bits < 16);
tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addr, a_mask);
ldst->label_ptr[0] = s->code_ptr; ldst->label_ptr[0] = s->code_ptr;
if (use_mips32r6_instructions) { if (use_mips32r6_instructions) {
@ -1340,7 +1324,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
} }
} }
base = addrlo; base = addr;
if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
tcg_out_ext32u(s, TCG_REG_A0, base); tcg_out_ext32u(s, TCG_REG_A0, base);
base = TCG_REG_A0; base = TCG_REG_A0;
@ -1460,14 +1444,13 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
} }
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
TCGReg addrlo, TCGReg addrhi, TCGReg addr, MemOpIdx oi, TCGType data_type)
MemOpIdx oi, TCGType data_type)
{ {
MemOp opc = get_memop(oi); MemOp opc = get_memop(oi);
TCGLabelQemuLdst *ldst; TCGLabelQemuLdst *ldst;
HostAddress h; HostAddress h;
ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true); ldst = prepare_host_addr(s, &h, addr, oi, true);
if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type);
@ -1547,14 +1530,13 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
} }
static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
TCGReg addrlo, TCGReg addrhi, TCGReg addr, MemOpIdx oi, TCGType data_type)
MemOpIdx oi, TCGType data_type)
{ {
MemOp opc = get_memop(oi); MemOp opc = get_memop(oi);
TCGLabelQemuLdst *ldst; TCGLabelQemuLdst *ldst;
HostAddress h; HostAddress h;
ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false); ldst = prepare_host_addr(s, &h, addr, oi, false);
if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc);
@ -2096,24 +2078,24 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
break; break;
case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i32:
tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I32);
break; break;
case INDEX_op_qemu_ld_i64: case INDEX_op_qemu_ld_i64:
if (TCG_TARGET_REG_BITS == 64) { if (TCG_TARGET_REG_BITS == 64) {
tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I64);
} else { } else {
tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64);
} }
break; break;
case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i32:
tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I32);
break; break;
case INDEX_op_qemu_st_i64: case INDEX_op_qemu_st_i64:
if (TCG_TARGET_REG_BITS == 64) { if (TCG_TARGET_REG_BITS == 64) {
tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I64);
} else { } else {
tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64);
} }
break; break;