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target/riscv: Implement optional CSR mcontext of debug Sdtrig extension

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The debug Sdtrig extension defines an CSR "mcontext". This commit
implements its predicate and read/write operations into CSR table.
Its value is reset as 0 when the trigger module is reset.

Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20231219123244.290935-1-alvinga@andestech.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Alvin Chang 2023-12-19 20:32:44 +08:00 committed by Alistair Francis
parent 10efbe01ce
commit 0c4e579aac
4 changed files with 41 additions and 5 deletions
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1
target/riscv/cpu.h
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@ -365,6 +365,7 @@ struct CPUArchState {
target_ulong tdata1[RV_MAX_TRIGGERS]; target_ulong tdata1[RV_MAX_TRIGGERS];
target_ulong tdata2[RV_MAX_TRIGGERS]; target_ulong tdata2[RV_MAX_TRIGGERS];
target_ulong tdata3[RV_MAX_TRIGGERS]; target_ulong tdata3[RV_MAX_TRIGGERS];
target_ulong mcontext;
struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS];
struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS];

7
target/riscv/cpu_bits.h
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@ -361,6 +361,7 @@
#define CSR_TDATA2 0x7a2 #define CSR_TDATA2 0x7a2
#define CSR_TDATA3 0x7a3 #define CSR_TDATA3 0x7a3
#define CSR_TINFO 0x7a4 #define CSR_TINFO 0x7a4
#define CSR_MCONTEXT 0x7a8
/* Debug Mode Registers */ /* Debug Mode Registers */
#define CSR_DCSR 0x7b0 #define CSR_DCSR 0x7b0
@ -905,4 +906,10 @@ typedef enum RISCVException {
/* JVT CSR bits */ /* JVT CSR bits */
#define JVT_MODE 0x3F #define JVT_MODE 0x3F
#define JVT_BASE (~0x3F) #define JVT_BASE (~0x3F)
/* Debug Sdtrig CSR masks */
#define MCONTEXT32 0x0000003F
#define MCONTEXT64 0x0000000000001FFFULL
#define MCONTEXT32_HCONTEXT 0x0000007F
#define MCONTEXT64_HCONTEXT 0x0000000000003FFFULL
#endif #endif

36
target/riscv/csr.c
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@ -3906,6 +3906,31 @@ static RISCVException read_tinfo(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE; return RISCV_EXCP_NONE;
} }
static RISCVException read_mcontext(CPURISCVState *env, int csrno,
target_ulong *val)
{
*val = env->mcontext;
return RISCV_EXCP_NONE;
}
static RISCVException write_mcontext(CPURISCVState *env, int csrno,
target_ulong val)
{
bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false;
int32_t mask;
if (riscv_has_ext(env, RVH)) {
/* Spec suggest 7-bit for RV32 and 14-bit for RV64 w/ H extension */
mask = rv32 ? MCONTEXT32_HCONTEXT : MCONTEXT64_HCONTEXT;
} else {
/* Spec suggest 6-bit for RV32 and 13-bit for RV64 w/o H extension */
mask = rv32 ? MCONTEXT32 : MCONTEXT64;
}
env->mcontext = val & mask;
return RISCV_EXCP_NONE;
}
/* /*
* Functions to access Pointer Masking feature registers * Functions to access Pointer Masking feature registers
* We have to check if current priv lvl could modify * We have to check if current priv lvl could modify
@ -4800,11 +4825,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, [CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
/* Debug CSRs */ /* Debug CSRs */
[CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect }, [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect },
[CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata }, [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata },
[CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata }, [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata },
[CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata }, [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata },
[CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore }, [CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore },
[CSR_MCONTEXT] = { "mcontext", debug, read_mcontext, write_mcontext },
/* User Pointer Masking */ /* User Pointer Masking */
[CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte }, [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },

2
target/riscv/debug.c
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@ -940,4 +940,6 @@ void riscv_trigger_reset_hold(CPURISCVState *env)
env->cpu_watchpoint[i] = NULL; env->cpu_watchpoint[i] = NULL;
timer_del(env->itrigger_timer[i]); timer_del(env->itrigger_timer[i]);
} }
env->mcontext = 0;
} }