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target/arm: Move RME TLB insns to tlb-insns.c

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Move the FEAT_RME specific TLB insns across to tlb-insns.c.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241210160452.2427965-10-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2024-12-10 16:04:51 +00:00
parent 27fb860fd4
commit 0b7aefb9eb
2 changed files with 45 additions and 38 deletions
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38
target/arm/helper.c
View File

@ -6525,14 +6525,6 @@ static const ARMCPRegInfo sme_reginfo[] = {
.type = ARM_CP_CONST, .resetvalue = 0 }, .type = ARM_CP_CONST, .resetvalue = 0 },
}; };
static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
CPUState *cs = env_cpu(env);
tlb_flush(cs);
}
static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void gpccr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
@ -6550,14 +6542,6 @@ static void gpccr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
env_archcpu(env)->reset_l0gptsz); env_archcpu(env)->reset_l0gptsz);
} }
static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
CPUState *cs = env_cpu(env);
tlb_flush_all_cpus_synced(cs);
}
static const ARMCPRegInfo rme_reginfo[] = { static const ARMCPRegInfo rme_reginfo[] = {
{ .name = "GPCCR_EL3", .state = ARM_CP_STATE_AA64, { .name = "GPCCR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 6, .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 1, .opc2 = 6,
@ -6569,28 +6553,6 @@ static const ARMCPRegInfo rme_reginfo[] = {
{ .name = "MFAR_EL3", .state = ARM_CP_STATE_AA64, { .name = "MFAR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 5, .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 5,
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mfar_el3) }, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mfar_el3) },
{ .name = "TLBI_PAALL", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 4,
.access = PL3_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_paall_write },
{ .name = "TLBI_PAALLOS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 4,
.access = PL3_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_paallos_write },
/*
* QEMU does not have a way to invalidate by physical address, thus
* invalidating a range of physical addresses is accomplished by
* flushing all tlb entries in the outer shareable domain,
* just like PAALLOS.
*/
{ .name = "TLBI_RPALOS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 7,
.access = PL3_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_paallos_write },
{ .name = "TLBI_RPAOS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 3,
.access = PL3_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_paallos_write },
{ .name = "DC_CIPAPA", .state = ARM_CP_STATE_AA64, { .name = "DC_CIPAPA", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 1, .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 14, .opc2 = 1,
.access = PL3_W, .type = ARM_CP_NOP }, .access = PL3_W, .type = ARM_CP_NOP },

45
target/arm/tcg/tlb-insns.c
View File

@ -1181,6 +1181,48 @@ static const ARMCPRegInfo tlbios_reginfo[] = {
.access = PL3_W, .type = ARM_CP_NO_RAW, .access = PL3_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae3is_write }, .writefn = tlbi_aa64_vae3is_write },
}; };
static void tlbi_aa64_paall_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
CPUState *cs = env_cpu(env);
tlb_flush(cs);
}
static void tlbi_aa64_paallos_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
CPUState *cs = env_cpu(env);
tlb_flush_all_cpus_synced(cs);
}
static const ARMCPRegInfo tlbi_rme_reginfo[] = {
{ .name = "TLBI_PAALL", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 4,
.access = PL3_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_paall_write },
{ .name = "TLBI_PAALLOS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 1, .opc2 = 4,
.access = PL3_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_paallos_write },
/*
* QEMU does not have a way to invalidate by physical address, thus
* invalidating a range of physical addresses is accomplished by
* flushing all tlb entries in the outer shareable domain,
* just like PAALLOS.
*/
{ .name = "TLBI_RPALOS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 7,
.access = PL3_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_paallos_write },
{ .name = "TLBI_RPAOS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 6, .crn = 8, .crm = 4, .opc2 = 3,
.access = PL3_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_paallos_write },
};
#endif #endif
void define_tlb_insn_regs(ARMCPU *cpu) void define_tlb_insn_regs(ARMCPU *cpu)
@ -1219,5 +1261,8 @@ void define_tlb_insn_regs(ARMCPU *cpu)
if (cpu_isar_feature(aa64_tlbios, cpu)) { if (cpu_isar_feature(aa64_tlbios, cpu)) {
define_arm_cp_regs(cpu, tlbios_reginfo); define_arm_cp_regs(cpu, tlbios_reginfo);
} }
if (cpu_isar_feature(aa64_rme, cpu)) {
define_arm_cp_regs(cpu, tlbi_rme_reginfo);
}
#endif #endif
} }