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target-arm queue:

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* hw/sd: Fix sun4i allwinner-sdhost for U-Boot
  * hw/intc: add implementation of GICD_IIDR to Arm GIC
  * tests/avocado/boot_linux.py: Bump aarch64 virt test timeout
  * target/arm: Limit LPA2 effective output address when TCR.DS == 0
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Merge tag 'pull-target-arm-20221121' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * hw/sd: Fix sun4i allwinner-sdhost for U-Boot
 * hw/intc: add implementation of GICD_IIDR to Arm GIC
 * tests/avocado/boot_linux.py: Bump aarch64 virt test timeout
 * target/arm: Limit LPA2 effective output address when TCR.DS == 0

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# gpg: Signature made Mon 21 Nov 2022 07:59:23 EST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20221121' of https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: Limit LPA2 effective output address when TCR.DS == 0
  tests/avocado/boot_linux.py: Bump aarch64 virt test timeout to 720s
  hw/intc: add implementation of GICD_IIDR to Arm GIC
  hw/intc: clean-up access to GIC multi-byte registers
  hw/sd: Fix sun4i allwinner-sdhost for U-Boot

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2022-11-21 09:26:34 -05:00
commit 0b710ae5c5
5 changed files with 77 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
hw/intc/arm_gic.c
View File

@ -941,7 +941,7 @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
gic_update(s); gic_update(s);
} }
static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs) static uint8_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
{ {
GICState *s = (GICState *)opaque; GICState *s = (GICState *)opaque;
uint32_t res; uint32_t res;
@ -955,6 +955,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
cm = 1 << cpu; cm = 1 << cpu;
if (offset < 0x100) { if (offset < 0x100) {
if (offset == 0) { /* GICD_CTLR */ if (offset == 0) { /* GICD_CTLR */
/* We rely here on the only non-zero bits being in byte 0 */
if (s->security_extn && !attrs.secure) { if (s->security_extn && !attrs.secure) {
/* The NS bank of this register is just an alias of the /* The NS bank of this register is just an alias of the
* EnableGrp1 bit in the S bank version. * EnableGrp1 bit in the S bank version.
@ -964,13 +965,26 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
return s->ctlr; return s->ctlr;
} }
} }
if (offset == 4) if (offset == 4) {
/* Interrupt Controller Type Register */ /* GICD_TYPER byte 0 */
return ((s->num_irq / 32) - 1) return ((s->num_irq / 32) - 1) | ((s->num_cpu - 1) << 5);
| ((s->num_cpu - 1) << 5) }
| (s->security_extn << 10); if (offset == 5) {
if (offset < 0x08) /* GICD_TYPER byte 1 */
return (s->security_extn << 2);
}
if (offset == 8) {
/* GICD_IIDR byte 0 */
return 0x3b; /* Arm JEP106 identity */
}
if (offset == 9) {
/* GICD_IIDR byte 1 */
return 0x04; /* Arm JEP106 identity */
}
if (offset < 0x0c) {
/* All other bytes in this range are RAZ */
return 0; return 0;
}
if (offset >= 0x80) { if (offset >= 0x80) {
/* Interrupt Group Registers: these RAZ/WI if this is an NS /* Interrupt Group Registers: these RAZ/WI if this is an NS
* access to a GIC with the security extensions, or if the GIC * access to a GIC with the security extensions, or if the GIC

63
hw/sd/allwinner-sdhost.c
View File

@ -65,7 +65,7 @@ enum {
REG_SD_DLBA = 0x84, /* Descriptor List Base Address */ REG_SD_DLBA = 0x84, /* Descriptor List Base Address */
REG_SD_IDST = 0x88, /* Internal DMA Controller Status */ REG_SD_IDST = 0x88, /* Internal DMA Controller Status */
REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */ REG_SD_IDIE = 0x8C, /* Internal DMA Controller IRQ Enable */
REG_SD_THLDC = 0x100, /* Card Threshold Control */ REG_SD_THLDC = 0x100, /* Card Threshold Control / FIFO (sun4i only)*/
REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */ REG_SD_DSBD = 0x10C, /* eMMC DDR Start Bit Detection Control */
REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */ REG_SD_RES_CRC = 0x110, /* Response CRC from card/eMMC */
REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */ REG_SD_DATA7_CRC = 0x114, /* CRC Data 7 from card/eMMC */
@ -415,10 +415,29 @@ static void allwinner_sdhost_dma(AwSdHostState *s)
} }
} }
static uint32_t allwinner_sdhost_fifo_read(AwSdHostState *s)
{
uint32_t res = 0;
if (sdbus_data_ready(&s->sdbus)) {
sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
le32_to_cpus(&res);
allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
allwinner_sdhost_auto_stop(s);
allwinner_sdhost_update_irq(s);
} else {
qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
__func__);
}
return res;
}
static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset, static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
unsigned size) unsigned size)
{ {
AwSdHostState *s = AW_SDHOST(opaque); AwSdHostState *s = AW_SDHOST(opaque);
AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
uint32_t res = 0; uint32_t res = 0;
switch (offset) { switch (offset) {
@ -508,8 +527,12 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */ case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
res = s->dmac_irq; res = s->dmac_irq;
break; break;
case REG_SD_THLDC: /* Card Threshold Control */ case REG_SD_THLDC: /* Card Threshold Control or FIFO register (sun4i) */
if (sc->is_sun4i) {
res = allwinner_sdhost_fifo_read(s);
} else {
res = s->card_threshold; res = s->card_threshold;
}
break; break;
case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
res = s->startbit_detect; res = s->startbit_detect;
@ -531,16 +554,7 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
res = s->status_crc; res = s->status_crc;
break; break;
case REG_SD_FIFO: /* Read/Write FIFO */ case REG_SD_FIFO: /* Read/Write FIFO */
if (sdbus_data_ready(&s->sdbus)) { res = allwinner_sdhost_fifo_read(s);
sdbus_read_data(&s->sdbus, &res, sizeof(uint32_t));
le32_to_cpus(&res);
allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
allwinner_sdhost_auto_stop(s);
allwinner_sdhost_update_irq(s);
} else {
qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
__func__);
}
break; break;
default: default:
qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %" qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
@ -553,11 +567,20 @@ static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
return res; return res;
} }
static void allwinner_sdhost_fifo_write(AwSdHostState *s, uint64_t value)
{
uint32_t u32 = cpu_to_le32(value);
sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
allwinner_sdhost_auto_stop(s);
allwinner_sdhost_update_irq(s);
}
static void allwinner_sdhost_write(void *opaque, hwaddr offset, static void allwinner_sdhost_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size) uint64_t value, unsigned size)
{ {
AwSdHostState *s = AW_SDHOST(opaque); AwSdHostState *s = AW_SDHOST(opaque);
uint32_t u32; AwSdHostClass *sc = AW_SDHOST_GET_CLASS(s);
trace_allwinner_sdhost_write(offset, value, size); trace_allwinner_sdhost_write(offset, value, size);
@ -657,18 +680,18 @@ static void allwinner_sdhost_write(void *opaque, hwaddr offset,
s->dmac_irq = value; s->dmac_irq = value;
allwinner_sdhost_update_irq(s); allwinner_sdhost_update_irq(s);
break; break;
case REG_SD_THLDC: /* Card Threshold Control */ case REG_SD_THLDC: /* Card Threshold Control or FIFO (sun4i) */
if (sc->is_sun4i) {
allwinner_sdhost_fifo_write(s, value);
} else {
s->card_threshold = value; s->card_threshold = value;
}
break; break;
case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */ case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
s->startbit_detect = value; s->startbit_detect = value;
break; break;
case REG_SD_FIFO: /* Read/Write FIFO */ case REG_SD_FIFO: /* Read/Write FIFO */
u32 = cpu_to_le32(value); allwinner_sdhost_fifo_write(s, value);
sdbus_write_data(&s->sdbus, &u32, sizeof(u32));
allwinner_sdhost_update_transfer_cnt(s, sizeof(u32));
allwinner_sdhost_auto_stop(s);
allwinner_sdhost_update_irq(s);
break; break;
case REG_SD_RES_CRC: /* Response CRC from card/eMMC */ case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */ case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
@ -834,12 +857,14 @@ static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *data)
{ {
AwSdHostClass *sc = AW_SDHOST_CLASS(klass); AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
sc->max_desc_size = 8 * KiB; sc->max_desc_size = 8 * KiB;
sc->is_sun4i = true;
} }
static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data) static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *data)
{ {
AwSdHostClass *sc = AW_SDHOST_CLASS(klass); AwSdHostClass *sc = AW_SDHOST_CLASS(klass);
sc->max_desc_size = 64 * KiB; sc->max_desc_size = 64 * KiB;
sc->is_sun4i = false;
} }
static const TypeInfo allwinner_sdhost_info = { static const TypeInfo allwinner_sdhost_info = {

1
include/hw/sd/allwinner-sdhost.h
View File

@ -130,6 +130,7 @@ struct AwSdHostClass {
/** Maximum buffer size in bytes per DMA descriptor */ /** Maximum buffer size in bytes per DMA descriptor */
size_t max_desc_size; size_t max_desc_size;
bool is_sun4i;
}; };

8
target/arm/ptw.c
View File

@ -1222,6 +1222,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
ps = MIN(ps, param.ps); ps = MIN(ps, param.ps);
assert(ps < ARRAY_SIZE(pamax_map)); assert(ps < ARRAY_SIZE(pamax_map));
outputsize = pamax_map[ps]; outputsize = pamax_map[ps];
/*
* With LPA2, the effective output address (OA) size is at most 48 bits
* unless TCR.DS == 1
*/
if (!param.ds && param.gran != Gran64K) {
outputsize = MIN(outputsize, 48);
}
} else { } else {
param = aa32_va_parameters(env, address, mmu_idx); param = aa32_va_parameters(env, address, mmu_idx);
level = 1; level = 1;

2
tests/avocado/boot_linux.py
View File

@ -64,7 +64,7 @@ class BootLinuxAarch64(LinuxTest):
:avocado: tags=machine:virt :avocado: tags=machine:virt
:avocado: tags=machine:gic-version=2 :avocado: tags=machine:gic-version=2
""" """
timeout = 240 timeout = 720
def add_common_args(self): def add_common_args(self):
self.vm.add_args('-bios', self.vm.add_args('-bios',