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target/arm: Mark LDS{MIN,MAX} as signed operations

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The operands to tcg_gen_atomic_fetch_s{min,max}_i64 must
be signed, so that the inputs are properly extended.
Zero extend the result afterward, as needed.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/364
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20210602020720.47679-1-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2021-06-01 19:07:20 -07:00 committed by Peter Maydell
parent 269a7e9786
commit 0711a63435
1 changed files with 10 additions and 3 deletions
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13
target/arm/translate-a64.c
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@ -3355,8 +3355,9 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
int o3_opc = extract32(insn, 12, 4); int o3_opc = extract32(insn, 12, 4);
bool r = extract32(insn, 22, 1); bool r = extract32(insn, 22, 1);
bool a = extract32(insn, 23, 1); bool a = extract32(insn, 23, 1);
TCGv_i64 tcg_rs, clean_addr; TCGv_i64 tcg_rs, tcg_rt, clean_addr;
AtomicThreeOpFn *fn = NULL; AtomicThreeOpFn *fn = NULL;
MemOp mop = s->be_data | size | MO_ALIGN;
if (is_vector || !dc_isar_feature(aa64_atomics, s)) { if (is_vector || !dc_isar_feature(aa64_atomics, s)) {
unallocated_encoding(s); unallocated_encoding(s);
@ -3377,9 +3378,11 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
break; break;
case 004: /* LDSMAX */ case 004: /* LDSMAX */
fn = tcg_gen_atomic_fetch_smax_i64; fn = tcg_gen_atomic_fetch_smax_i64;
mop |= MO_SIGN;
break; break;
case 005: /* LDSMIN */ case 005: /* LDSMIN */
fn = tcg_gen_atomic_fetch_smin_i64; fn = tcg_gen_atomic_fetch_smin_i64;
mop |= MO_SIGN;
break; break;
case 006: /* LDUMAX */ case 006: /* LDUMAX */
fn = tcg_gen_atomic_fetch_umax_i64; fn = tcg_gen_atomic_fetch_umax_i64;
@ -3422,6 +3425,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
} }
tcg_rs = read_cpu_reg(s, rs, true); tcg_rs = read_cpu_reg(s, rs, true);
tcg_rt = cpu_reg(s, rt);
if (o3_opc == 1) { /* LDCLR */ if (o3_opc == 1) { /* LDCLR */
tcg_gen_not_i64(tcg_rs, tcg_rs); tcg_gen_not_i64(tcg_rs, tcg_rs);
@ -3430,8 +3434,11 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
/* The tcg atomic primitives are all full barriers. Therefore we /* The tcg atomic primitives are all full barriers. Therefore we
* can ignore the Acquire and Release bits of this instruction. * can ignore the Acquire and Release bits of this instruction.
*/ */
fn(cpu_reg(s, rt), clean_addr, tcg_rs, get_mem_index(s), fn(tcg_rt, clean_addr, tcg_rs, get_mem_index(s), mop);
s->be_data | size | MO_ALIGN);
if ((mop & MO_SIGN) && size != MO_64) {
tcg_gen_ext32u_i64(tcg_rt, tcg_rt);
}
} }
/* /*