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target/riscv: Use tcg_constant_*

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Replace uses of tcg_const_* with the allocate and free close together.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210823195529.560295-2-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Richard Henderson 2021-08-23 12:55:06 -07:00 committed by Alistair Francis
parent 2a4b408930
commit 05b80ed0a1
3 changed files with 34 additions and 70 deletions
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3
target/riscv/insn_trans/trans_rvf.c.inc
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@ -200,12 +200,11 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
* Replace bit 31 in rs1 with inverse in rs2. * Replace bit 31 in rs1 with inverse in rs2.
* This formulation retains the nanboxing of rs1. * This formulation retains the nanboxing of rs1.
*/ */
mask = tcg_const_i64(~MAKE_64BIT_MASK(31, 1)); mask = tcg_constant_i64(~MAKE_64BIT_MASK(31, 1));
tcg_gen_nor_i64(rs2, rs2, mask); tcg_gen_nor_i64(rs2, rs2, mask);
tcg_gen_and_i64(rs1, mask, rs1); tcg_gen_and_i64(rs1, mask, rs1);
tcg_gen_or_i64(cpu_fpr[a->rd], rs1, rs2); tcg_gen_or_i64(cpu_fpr[a->rd], rs1, rs2);
tcg_temp_free_i64(mask);
tcg_temp_free_i64(rs2); tcg_temp_free_i64(rs2);
} }
tcg_temp_free_i64(rs1); tcg_temp_free_i64(rs1);

63
target/riscv/insn_trans/trans_rvv.c.inc
View File

@ -33,7 +33,7 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
/* Using x0 as the rs1 register specifier, encodes an infinite AVL */ /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
if (a->rs1 == 0) { if (a->rs1 == 0) {
/* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */ /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
s1 = tcg_const_tl(RV_VLEN_MAX); s1 = tcg_constant_tl(RV_VLEN_MAX);
} else { } else {
s1 = tcg_temp_new(); s1 = tcg_temp_new();
gen_get_gpr(s1, a->rs1); gen_get_gpr(s1, a->rs1);
@ -59,13 +59,13 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
return false; return false;
} }
s2 = tcg_const_tl(a->zimm); s2 = tcg_constant_tl(a->zimm);
dst = tcg_temp_new(); dst = tcg_temp_new();
/* Using x0 as the rs1 register specifier, encodes an infinite AVL */ /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
if (a->rs1 == 0) { if (a->rs1 == 0) {
/* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */ /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
s1 = tcg_const_tl(RV_VLEN_MAX); s1 = tcg_constant_tl(RV_VLEN_MAX);
} else { } else {
s1 = tcg_temp_new(); s1 = tcg_temp_new();
gen_get_gpr(s1, a->rs1); gen_get_gpr(s1, a->rs1);
@ -76,7 +76,6 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
tcg_temp_free(s1); tcg_temp_free(s1);
tcg_temp_free(s2);
tcg_temp_free(dst); tcg_temp_free(dst);
return true; return true;
} }
@ -183,7 +182,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
* The first part is vlen in bytes, encoded in maxsz of simd_desc. * The first part is vlen in bytes, encoded in maxsz of simd_desc.
* The second part is lmul, encoded in data of simd_desc. * The second part is lmul, encoded in data of simd_desc.
*/ */
desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
gen_get_gpr(base, rs1); gen_get_gpr(base, rs1);
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@ -194,7 +193,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
tcg_temp_free_ptr(dest); tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask); tcg_temp_free_ptr(mask);
tcg_temp_free(base); tcg_temp_free(base);
tcg_temp_free_i32(desc);
gen_set_label(over); gen_set_label(over);
return true; return true;
} }
@ -334,7 +332,7 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
mask = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr();
base = tcg_temp_new(); base = tcg_temp_new();
stride = tcg_temp_new(); stride = tcg_temp_new();
desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
gen_get_gpr(base, rs1); gen_get_gpr(base, rs1);
gen_get_gpr(stride, rs2); gen_get_gpr(stride, rs2);
@ -347,7 +345,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
tcg_temp_free_ptr(mask); tcg_temp_free_ptr(mask);
tcg_temp_free(base); tcg_temp_free(base);
tcg_temp_free(stride); tcg_temp_free(stride);
tcg_temp_free_i32(desc);
gen_set_label(over); gen_set_label(over);
return true; return true;
} }
@ -462,7 +459,7 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
mask = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr();
index = tcg_temp_new_ptr(); index = tcg_temp_new_ptr();
base = tcg_temp_new(); base = tcg_temp_new();
desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
gen_get_gpr(base, rs1); gen_get_gpr(base, rs1);
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@ -475,7 +472,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
tcg_temp_free_ptr(mask); tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(index); tcg_temp_free_ptr(index);
tcg_temp_free(base); tcg_temp_free(base);
tcg_temp_free_i32(desc);
gen_set_label(over); gen_set_label(over);
return true; return true;
} }
@ -594,7 +590,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
dest = tcg_temp_new_ptr(); dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr();
base = tcg_temp_new(); base = tcg_temp_new();
desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
gen_get_gpr(base, rs1); gen_get_gpr(base, rs1);
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@ -605,7 +601,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
tcg_temp_free_ptr(dest); tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask); tcg_temp_free_ptr(mask);
tcg_temp_free(base); tcg_temp_free(base);
tcg_temp_free_i32(desc);
gen_set_label(over); gen_set_label(over);
return true; return true;
} }
@ -671,7 +666,7 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
mask = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr();
index = tcg_temp_new_ptr(); index = tcg_temp_new_ptr();
base = tcg_temp_new(); base = tcg_temp_new();
desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
gen_get_gpr(base, rs1); gen_get_gpr(base, rs1);
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
@ -684,7 +679,6 @@ static bool amo_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
tcg_temp_free_ptr(mask); tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(index); tcg_temp_free_ptr(index);
tcg_temp_free(base); tcg_temp_free(base);
tcg_temp_free_i32(desc);
gen_set_label(over); gen_set_label(over);
return true; return true;
} }
@ -874,7 +868,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, vm); data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@ -886,7 +880,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
tcg_temp_free_ptr(mask); tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(src2); tcg_temp_free_ptr(src2);
tcg_temp_free(src1); tcg_temp_free(src1);
tcg_temp_free_i32(desc);
gen_set_label(over); gen_set_label(over);
return true; return true;
} }
@ -1014,14 +1007,14 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
mask = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr(); src2 = tcg_temp_new_ptr();
if (zx) { if (zx) {
src1 = tcg_const_tl(imm); src1 = tcg_constant_tl(imm);
} else { } else {
src1 = tcg_const_tl(sextract64(imm, 0, 5)); src1 = tcg_constant_tl(sextract64(imm, 0, 5));
} }
data = FIELD_DP32(data, VDATA, MLEN, s->mlen); data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, vm); data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@ -1032,8 +1025,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
tcg_temp_free_ptr(dest); tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask); tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(src2); tcg_temp_free_ptr(src2);
tcg_temp_free(src1);
tcg_temp_free_i32(desc);
gen_set_label(over); gen_set_label(over);
return true; return true;
} }
@ -1080,9 +1071,8 @@ GEN_OPIVI_GVEC_TRANS(vadd_vi, 0, vadd_vx, addi)
static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs, static void tcg_gen_gvec_rsubi(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t c, uint32_t oprsz, uint32_t maxsz) int64_t c, uint32_t oprsz, uint32_t maxsz)
{ {
TCGv_i64 tmp = tcg_const_i64(c); TCGv_i64 tmp = tcg_constant_i64(c);
tcg_gen_gvec_rsubs(vece, dofs, aofs, tmp, oprsz, maxsz); tcg_gen_gvec_rsubs(vece, dofs, aofs, tmp, oprsz, maxsz);
tcg_temp_free_i64(tmp);
} }
GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi) GEN_OPIVI_GVEC_TRANS(vrsub_vi, 0, vrsub_vx, rsubi)
@ -1692,12 +1682,11 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
}; };
tcg_gen_ext_tl_i64(s1_i64, s1); tcg_gen_ext_tl_i64(s1_i64, s1);
desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
fns[s->sew](dest, s1_i64, cpu_env, desc); fns[s->sew](dest, s1_i64, cpu_env, desc);
tcg_temp_free_ptr(dest); tcg_temp_free_ptr(dest);
tcg_temp_free_i32(desc);
tcg_temp_free_i64(s1_i64); tcg_temp_free_i64(s1_i64);
} }
@ -1729,15 +1718,13 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
TCGLabel *over = gen_new_label(); TCGLabel *over = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
s1 = tcg_const_i64(simm); s1 = tcg_constant_i64(simm);
dest = tcg_temp_new_ptr(); dest = tcg_temp_new_ptr();
desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
fns[s->sew](dest, s1, cpu_env, desc); fns[s->sew](dest, s1, cpu_env, desc);
tcg_temp_free_ptr(dest); tcg_temp_free_ptr(dest);
tcg_temp_free_i32(desc);
tcg_temp_free_i64(s1);
gen_set_label(over); gen_set_label(over);
} }
return true; return true;
@ -1866,7 +1853,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
dest = tcg_temp_new_ptr(); dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr(); src2 = tcg_temp_new_ptr();
desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, vs2));
@ -1877,7 +1864,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
tcg_temp_free_ptr(dest); tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask); tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(src2); tcg_temp_free_ptr(src2);
tcg_temp_free_i32(desc);
gen_set_label(over); gen_set_label(over);
return true; return true;
} }
@ -2231,12 +2217,11 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
dest = tcg_temp_new_ptr(); dest = tcg_temp_new_ptr();
desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd)); tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc); fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
tcg_temp_free_ptr(dest); tcg_temp_free_ptr(dest);
tcg_temp_free_i32(desc);
gen_set_label(over); gen_set_label(over);
} }
return true; return true;
@ -2428,7 +2413,7 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
mask = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr(); src2 = tcg_temp_new_ptr();
dst = tcg_temp_new(); dst = tcg_temp_new();
desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@ -2439,7 +2424,6 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
tcg_temp_free_ptr(mask); tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(src2); tcg_temp_free_ptr(src2);
tcg_temp_free(dst); tcg_temp_free(dst);
tcg_temp_free_i32(desc);
return true; return true;
} }
return false; return false;
@ -2460,7 +2444,7 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
mask = tcg_temp_new_ptr(); mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr(); src2 = tcg_temp_new_ptr();
dst = tcg_temp_new(); dst = tcg_temp_new();
desc = tcg_const_i32(simd_desc(s->vlen / 8, s->vlen / 8, data)); desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2)); tcg_gen_addi_ptr(src2, cpu_env, vreg_ofs(s, a->rs2));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@ -2471,7 +2455,6 @@ static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
tcg_temp_free_ptr(mask); tcg_temp_free_ptr(mask);
tcg_temp_free_ptr(src2); tcg_temp_free_ptr(src2);
tcg_temp_free(dst); tcg_temp_free(dst);
tcg_temp_free_i32(desc);
return true; return true;
} }
return false; return false;
@ -2636,15 +2619,13 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64 dest,
tcg_temp_free_i32(ofs); tcg_temp_free_i32(ofs);
/* Flush out-of-range indexing to zero. */ /* Flush out-of-range indexing to zero. */
t_vlmax = tcg_const_i64(vlmax); t_vlmax = tcg_constant_i64(vlmax);
t_zero = tcg_const_i64(0); t_zero = tcg_constant_i64(0);
tcg_gen_extu_tl_i64(t_idx, idx); tcg_gen_extu_tl_i64(t_idx, idx);
tcg_gen_movcond_i64(TCG_COND_LTU, dest, t_idx, tcg_gen_movcond_i64(TCG_COND_LTU, dest, t_idx,
t_vlmax, dest, t_zero); t_vlmax, dest, t_zero);
tcg_temp_free_i64(t_vlmax);
tcg_temp_free_i64(t_zero);
tcg_temp_free_i64(t_idx); tcg_temp_free_i64(t_idx);
} }

36
target/riscv/translate.c
View File

@ -104,20 +104,16 @@ static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
*/ */
static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
{ {
TCGv_i64 t_max = tcg_const_i64(0xffffffff00000000ull); TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull);
TCGv_i64 t_nan = tcg_const_i64(0xffffffff7fc00000ull); TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull);
tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
tcg_temp_free_i64(t_max);
tcg_temp_free_i64(t_nan);
} }
static void generate_exception(DisasContext *ctx, int excp) static void generate_exception(DisasContext *ctx, int excp)
{ {
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
TCGv_i32 helper_tmp = tcg_const_i32(excp); gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
gen_helper_raise_exception(cpu_env, helper_tmp);
tcg_temp_free_i32(helper_tmp);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
} }
@ -125,17 +121,13 @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
{ {
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
TCGv_i32 helper_tmp = tcg_const_i32(excp); gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
gen_helper_raise_exception(cpu_env, helper_tmp);
tcg_temp_free_i32(helper_tmp);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
} }
static void gen_exception_debug(void) static void gen_exception_debug(void)
{ {
TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG); gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
gen_helper_raise_exception(cpu_env, helper_tmp);
tcg_temp_free_i32(helper_tmp);
} }
/* Wrapper around tcg_gen_exit_tb that handles single stepping */ /* Wrapper around tcg_gen_exit_tb that handles single stepping */
@ -229,7 +221,7 @@ static void gen_div(TCGv ret, TCGv source1, TCGv source2)
*/ */
cond1 = tcg_temp_new(); cond1 = tcg_temp_new();
cond2 = tcg_temp_new(); cond2 = tcg_temp_new();
zeroreg = tcg_const_tl(0); zeroreg = tcg_constant_tl(0);
resultopt1 = tcg_temp_new(); resultopt1 = tcg_temp_new();
tcg_gen_movi_tl(resultopt1, (target_ulong)-1); tcg_gen_movi_tl(resultopt1, (target_ulong)-1);
@ -250,7 +242,6 @@ static void gen_div(TCGv ret, TCGv source1, TCGv source2)
tcg_temp_free(cond1); tcg_temp_free(cond1);
tcg_temp_free(cond2); tcg_temp_free(cond2);
tcg_temp_free(zeroreg);
tcg_temp_free(resultopt1); tcg_temp_free(resultopt1);
} }
@ -259,7 +250,7 @@ static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
TCGv cond1, zeroreg, resultopt1; TCGv cond1, zeroreg, resultopt1;
cond1 = tcg_temp_new(); cond1 = tcg_temp_new();
zeroreg = tcg_const_tl(0); zeroreg = tcg_constant_tl(0);
resultopt1 = tcg_temp_new(); resultopt1 = tcg_temp_new();
tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0);
@ -272,7 +263,6 @@ static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
tcg_gen_divu_tl(ret, source1, source2); tcg_gen_divu_tl(ret, source1, source2);
tcg_temp_free(cond1); tcg_temp_free(cond1);
tcg_temp_free(zeroreg);
tcg_temp_free(resultopt1); tcg_temp_free(resultopt1);
} }
@ -282,7 +272,7 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
cond1 = tcg_temp_new(); cond1 = tcg_temp_new();
cond2 = tcg_temp_new(); cond2 = tcg_temp_new();
zeroreg = tcg_const_tl(0); zeroreg = tcg_constant_tl(0);
resultopt1 = tcg_temp_new(); resultopt1 = tcg_temp_new();
tcg_gen_movi_tl(resultopt1, 1L); tcg_gen_movi_tl(resultopt1, 1L);
@ -302,7 +292,6 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
tcg_temp_free(cond1); tcg_temp_free(cond1);
tcg_temp_free(cond2); tcg_temp_free(cond2);
tcg_temp_free(zeroreg);
tcg_temp_free(resultopt1); tcg_temp_free(resultopt1);
} }
@ -310,7 +299,7 @@ static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
{ {
TCGv cond1, zeroreg, resultopt1; TCGv cond1, zeroreg, resultopt1;
cond1 = tcg_temp_new(); cond1 = tcg_temp_new();
zeroreg = tcg_const_tl(0); zeroreg = tcg_constant_tl(0);
resultopt1 = tcg_temp_new(); resultopt1 = tcg_temp_new();
tcg_gen_movi_tl(resultopt1, (target_ulong)1); tcg_gen_movi_tl(resultopt1, (target_ulong)1);
@ -323,7 +312,6 @@ static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
source1); source1);
tcg_temp_free(cond1); tcg_temp_free(cond1);
tcg_temp_free(zeroreg);
tcg_temp_free(resultopt1); tcg_temp_free(resultopt1);
} }
@ -384,15 +372,11 @@ static inline void mark_fs_dirty(DisasContext *ctx) { }
static void gen_set_rm(DisasContext *ctx, int rm) static void gen_set_rm(DisasContext *ctx, int rm)
{ {
TCGv_i32 t0;
if (ctx->frm == rm) { if (ctx->frm == rm) {
return; return;
} }
ctx->frm = rm; ctx->frm = rm;
t0 = tcg_const_i32(rm); gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
gen_helper_set_rounding_mode(cpu_env, t0);
tcg_temp_free_i32(t0);
} }
static int ex_plus_1(DisasContext *ctx, int nf) static int ex_plus_1(DisasContext *ctx, int nf)