i.MX: Standardize i.MX GPT debug
The goal is to have debug code always compiled during build. We standardize all debug output on the following format: [QOM_TYPE_NAME]reporting_function: debug message We also replace IPRINTF with qemu_log_mask(). The qemu_log_mask() output is following the same format as the above debug. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: b7ce7e98a051479453744aded122789531d80a44.1445781957.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -16,11 +16,17 @@
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#include "hw/misc/imx_ccm.h"
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#include "hw/misc/imx_ccm.h"
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#include "qemu/main-loop.h"
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#include "qemu/main-loop.h"
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/*
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#ifndef DEBUG_IMX_GPT
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* Define to 1 for debug messages
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#define DEBUG_IMX_GPT 0
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*/
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#endif
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#define DEBUG_TIMER 0
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#if DEBUG_TIMER
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#define DPRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX_GPT) { \
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fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPT, \
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__func__, ##args); \
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} \
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} while (0)
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static char const *imx_gpt_reg_name(uint32_t reg)
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static char const *imx_gpt_reg_name(uint32_t reg)
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{
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{
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@ -50,24 +56,6 @@ static char const *imx_gpt_reg_name(uint32_t reg)
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}
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}
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}
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}
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# define DPRINTF(fmt, args...) \
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do { printf("%s: " fmt , __func__, ##args); } while (0)
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#else
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# define DPRINTF(fmt, args...) do {} while (0)
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#endif
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/*
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* Define to 1 for messages about attempts to
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* access unimplemented registers or similar.
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*/
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#define DEBUG_IMPLEMENTATION 1
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#if DEBUG_IMPLEMENTATION
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# define IPRINTF(fmt, args...) \
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do { fprintf(stderr, "%s: " fmt, __func__, ##args); } while (0)
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#else
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# define IPRINTF(fmt, args...) do {} while (0)
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#endif
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static const VMStateDescription vmstate_imx_timer_gpt = {
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static const VMStateDescription vmstate_imx_timer_gpt = {
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.name = TYPE_IMX_GPT,
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.name = TYPE_IMX_GPT,
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.version_id = 3,
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.version_id = 3,
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@ -224,9 +212,8 @@ static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size)
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{
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{
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IMXGPTState *s = IMX_GPT(opaque);
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IMXGPTState *s = IMX_GPT(opaque);
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uint32_t reg_value = 0;
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uint32_t reg_value = 0;
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uint32_t reg = offset >> 2;
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switch (reg) {
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switch (offset >> 2) {
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case 0: /* Control Register */
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case 0: /* Control Register */
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reg_value = s->cr;
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reg_value = s->cr;
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break;
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break;
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@ -256,12 +243,14 @@ static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size)
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break;
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break;
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case 7: /* input Capture Register 1 */
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case 7: /* input Capture Register 1 */
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qemu_log_mask(LOG_UNIMP, "icr1 feature is not implemented\n");
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qemu_log_mask(LOG_UNIMP, "[%s]%s: icr1 feature is not implemented\n",
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TYPE_IMX_GPT, __func__);
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reg_value = s->icr1;
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reg_value = s->icr1;
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break;
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break;
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case 8: /* input Capture Register 2 */
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case 8: /* input Capture Register 2 */
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qemu_log_mask(LOG_UNIMP, "icr2 feature is not implemented\n");
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qemu_log_mask(LOG_UNIMP, "[%s]%s: icr2 feature is not implemented\n",
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TYPE_IMX_GPT, __func__);
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reg_value = s->icr2;
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reg_value = s->icr2;
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break;
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break;
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@ -271,11 +260,12 @@ static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size)
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break;
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break;
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default:
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default:
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IPRINTF("Bad offset %x\n", reg);
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
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break;
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break;
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}
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}
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DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(reg), reg_value);
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DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(offset >> 2), reg_value);
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return reg_value;
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return reg_value;
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}
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}
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@ -322,12 +312,11 @@ static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value,
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{
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{
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IMXGPTState *s = IMX_GPT(opaque);
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IMXGPTState *s = IMX_GPT(opaque);
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uint32_t oldreg;
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uint32_t oldreg;
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uint32_t reg = offset >> 2;
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DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(reg),
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DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(offset >> 2),
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(uint32_t)value);
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(uint32_t)value);
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switch (reg) {
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switch (offset >> 2) {
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case 0:
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case 0:
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oldreg = s->cr;
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oldreg = s->cr;
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s->cr = value & ~0x7c14;
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s->cr = value & ~0x7c14;
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@ -403,7 +392,8 @@ static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value,
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break;
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break;
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default:
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default:
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IPRINTF("Bad offset %x\n", reg);
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
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break;
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break;
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}
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}
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}
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}
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