FRET-LibAFL

History

Lucas Mateus Castro (alqotel) c29018cc73 target/ppc: Implemented xvf*ger*

Implement the following PowerISA v3.1 instructions:
xvf32ger:   VSX Vector 32-bit Floating-Point GER (rank-1 update)
xvf32gernn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Negative accumulate
xvf32gernp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Positive accumulate
xvf32gerpn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive
multiply, Negative accumulate
xvf32gerpp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive
multiply, Positive accumulate
xvf64ger:   VSX Vector 64-bit Floating-Point GER (rank-1 update)
xvf64gernn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative
multiply, Negative accumulate
xvf64gernp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative
multiply, Positive accumulate
xvf64gerpn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive
multiply, Negative accumulate
xvf64gerpp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive
multiply, Positive accumulate

Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220524140537.27451-5-lucas.araujo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>

2022-05-26 17:11:33 -03:00

branch-impl.c.inc

PPC64/TCG: Implement 'rfebb' instruction

2021-12-17 17:57:19 +01:00

dfp-impl.c.inc

target/ppc: Move ddedpd[q],denbcd[q],dscli[q],dscri[q] to decodetree

2021-11-09 10:32:52 +11:00

fixedpoint-impl.c.inc

exec/memop: Adding signedness to quad definitions

2022-01-08 15:46:10 +10:00

fp-impl.c.inc

target/ppc: Use TCG_CALL_NO_RWG_SE in fsel helper