6054fc73e8
The Aspeed I2C controller can operate in different transfer modes :
- Byte Buffer mode, using a dedicated register to transfer a
byte. This is what the model supports today.
- Pool Buffer mode, using an internal SRAM to transfer multiple
bytes in the same command sequence.
Each SoC has different SRAM characteristics. On the AST2400, 2048
bytes of SRAM are available at offset 0x800 of the controller AHB
window. The pool buffer can be configured from 1 to 256 bytes per bus.
On the AST2500, the SRAM is at offset 0x200 and the pool buffer is of
16 bytes per bus.
On the AST2600, the SRAM is at offset 0xC00 and the pool buffer is of
32 bytes per bus. It can be splitted in two for TX and RX but the
current model does not add support for it as it it unused by known
drivers.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-2-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
91 lines
2.4 KiB
C
91 lines
2.4 KiB
C
/*
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* ASPEED AST2400 I2C Controller
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*
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* Copyright (C) 2016 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef ASPEED_I2C_H
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#define ASPEED_I2C_H
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#include "hw/i2c/i2c.h"
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#include "hw/sysbus.h"
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#define TYPE_ASPEED_I2C "aspeed.i2c"
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#define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400"
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#define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500"
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#define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600"
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#define ASPEED_I2C(obj) \
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OBJECT_CHECK(AspeedI2CState, (obj), TYPE_ASPEED_I2C)
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#define ASPEED_I2C_NR_BUSSES 16
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#define ASPEED_I2C_MAX_POOL_SIZE 0x800
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struct AspeedI2CState;
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typedef struct AspeedI2CBus {
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struct AspeedI2CState *controller;
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MemoryRegion mr;
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I2CBus *bus;
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uint8_t id;
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qemu_irq irq;
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uint32_t ctrl;
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uint32_t timing[2];
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uint32_t intr_ctrl;
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uint32_t intr_status;
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uint32_t cmd;
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uint32_t buf;
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uint32_t pool_ctrl;
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} AspeedI2CBus;
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typedef struct AspeedI2CState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq irq;
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uint32_t intr_status;
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MemoryRegion pool_iomem;
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uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE];
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AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES];
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} AspeedI2CState;
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#define ASPEED_I2C_CLASS(klass) \
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OBJECT_CLASS_CHECK(AspeedI2CClass, (klass), TYPE_ASPEED_I2C)
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#define ASPEED_I2C_GET_CLASS(obj) \
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OBJECT_GET_CLASS(AspeedI2CClass, (obj), TYPE_ASPEED_I2C)
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typedef struct AspeedI2CClass {
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SysBusDeviceClass parent_class;
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uint8_t num_busses;
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uint8_t reg_size;
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uint8_t gap;
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qemu_irq (*bus_get_irq)(AspeedI2CBus *);
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uint64_t pool_size;
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hwaddr pool_base;
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uint8_t *(*bus_pool_base)(AspeedI2CBus *);
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} AspeedI2CClass;
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I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr);
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#endif /* ASPEED_I2C_H */
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