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tcg/tci: Remove tci_read_r32

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Use explicit casts for ext32u opcodes, and allow truncation
to happen for other users.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-01-29 11:28:43 -10:00
parent 994edd6719
commit 984ae87314
1 changed files with 54 additions and 68 deletions
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122
tcg/tci.c
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@ -64,11 +64,6 @@ static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index)
} }
#endif #endif
static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index)
{
return (uint32_t)tci_read_reg(regs, index);
}
#if TCG_TARGET_REG_BITS == 64 #if TCG_TARGET_REG_BITS == 64
static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index)
{ {
@ -145,22 +140,13 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
return value; return value;
} }
/* Read indexed register (32 bit) from bytecode. */
static uint32_t tci_read_r32(const tcg_target_ulong *regs,
const uint8_t **tb_ptr)
{
uint32_t value = tci_read_reg32(regs, **tb_ptr);
*tb_ptr += 1;
return value;
}
#if TCG_TARGET_REG_BITS == 32 #if TCG_TARGET_REG_BITS == 32
/* Read two indexed registers (2 * 32 bit) from bytecode. */ /* Read two indexed registers (2 * 32 bit) from bytecode. */
static uint64_t tci_read_r64(const tcg_target_ulong *regs, static uint64_t tci_read_r64(const tcg_target_ulong *regs,
const uint8_t **tb_ptr) const uint8_t **tb_ptr)
{ {
uint32_t low = tci_read_r32(regs, tb_ptr); uint32_t low = tci_read_r(regs, tb_ptr);
return tci_uint64(tci_read_r32(regs, tb_ptr), low); return tci_uint64(tci_read_r(regs, tb_ptr), low);
} }
#elif TCG_TARGET_REG_BITS == 64 #elif TCG_TARGET_REG_BITS == 64
/* Read indexed register (32 bit signed) from bytecode. */ /* Read indexed register (32 bit signed) from bytecode. */
@ -404,8 +390,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
continue; continue;
case INDEX_op_setcond_i32: case INDEX_op_setcond_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
condition = *tb_ptr++; condition = *tb_ptr++;
tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); tci_write_reg(regs, t0, tci_compare32(t1, t2, condition));
break; break;
@ -428,7 +414,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#endif #endif
case INDEX_op_mov_i32: case INDEX_op_mov_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1); tci_write_reg(regs, t0, t1);
break; break;
case INDEX_op_tci_movi_i32: case INDEX_op_tci_movi_i32:
@ -484,7 +470,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break; break;
case INDEX_op_st_i32: case INDEX_op_st_i32:
CASE_64(st32) CASE_64(st32)
t0 = tci_read_r32(regs, &tb_ptr); t0 = tci_read_r(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr); t2 = tci_read_s32(&tb_ptr);
*(uint32_t *)(t1 + t2) = t0; *(uint32_t *)(t1 + t2) = t0;
@ -494,62 +480,62 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_add_i32: case INDEX_op_add_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 + t2); tci_write_reg(regs, t0, t1 + t2);
break; break;
case INDEX_op_sub_i32: case INDEX_op_sub_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 - t2); tci_write_reg(regs, t0, t1 - t2);
break; break;
case INDEX_op_mul_i32: case INDEX_op_mul_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 * t2); tci_write_reg(regs, t0, t1 * t2);
break; break;
case INDEX_op_div_i32: case INDEX_op_div_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2);
break; break;
case INDEX_op_divu_i32: case INDEX_op_divu_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 / t2); tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2);
break; break;
case INDEX_op_rem_i32: case INDEX_op_rem_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2);
break; break;
case INDEX_op_remu_i32: case INDEX_op_remu_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 % t2); tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2);
break; break;
case INDEX_op_and_i32: case INDEX_op_and_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 & t2); tci_write_reg(regs, t0, t1 & t2);
break; break;
case INDEX_op_or_i32: case INDEX_op_or_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 | t2); tci_write_reg(regs, t0, t1 | t2);
break; break;
case INDEX_op_xor_i32: case INDEX_op_xor_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 ^ t2); tci_write_reg(regs, t0, t1 ^ t2);
break; break;
@ -557,41 +543,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_shl_i32: case INDEX_op_shl_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 << (t2 & 31)); tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31));
break; break;
case INDEX_op_shr_i32: case INDEX_op_shr_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 >> (t2 & 31)); tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31));
break; break;
case INDEX_op_sar_i32: case INDEX_op_sar_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, ((int32_t)t1 >> (t2 & 31))); tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31));
break; break;
#if TCG_TARGET_HAS_rot_i32 #if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32: case INDEX_op_rotl_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, rol32(t1, t2 & 31)); tci_write_reg(regs, t0, rol32(t1, t2 & 31));
break; break;
case INDEX_op_rotr_i32: case INDEX_op_rotr_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, ror32(t1, t2 & 31)); tci_write_reg(regs, t0, ror32(t1, t2 & 31));
break; break;
#endif #endif
#if TCG_TARGET_HAS_deposit_i32 #if TCG_TARGET_HAS_deposit_i32
case INDEX_op_deposit_i32: case INDEX_op_deposit_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tmp16 = *tb_ptr++; tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++; tmp8 = *tb_ptr++;
tmp32 = (((1 << tmp8) - 1) << tmp16); tmp32 = (((1 << tmp8) - 1) << tmp16);
@ -599,8 +585,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break; break;
#endif #endif
case INDEX_op_brcond_i32: case INDEX_op_brcond_i32:
t0 = tci_read_r32(regs, &tb_ptr); t0 = tci_read_r(regs, &tb_ptr);
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
condition = *tb_ptr++; condition = *tb_ptr++;
label = tci_read_label(&tb_ptr); label = tci_read_label(&tb_ptr);
if (tci_compare32(t0, t1, condition)) { if (tci_compare32(t0, t1, condition)) {
@ -638,9 +624,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_mulu2_i32: case INDEX_op_mulu2_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = *tb_ptr++; t1 = *tb_ptr++;
t2 = tci_read_r32(regs, &tb_ptr); t2 = tci_read_r(regs, &tb_ptr);
tmp64 = tci_read_r32(regs, &tb_ptr); tmp64 = (uint32_t)tci_read_r(regs, &tb_ptr);
tci_write_reg64(regs, t1, t0, t2 * tmp64); tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64);
break; break;
#endif /* TCG_TARGET_REG_BITS == 32 */ #endif /* TCG_TARGET_REG_BITS == 32 */
#if TCG_TARGET_HAS_ext8s_i32 #if TCG_TARGET_HAS_ext8s_i32
@ -681,21 +667,21 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_HAS_bswap32_i32 #if TCG_TARGET_HAS_bswap32_i32
case INDEX_op_bswap32_i32: case INDEX_op_bswap32_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap32(t1)); tci_write_reg(regs, t0, bswap32(t1));
break; break;
#endif #endif
#if TCG_TARGET_HAS_not_i32 #if TCG_TARGET_HAS_not_i32
case INDEX_op_not_i32: case INDEX_op_not_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, ~t1); tci_write_reg(regs, t0, ~t1);
break; break;
#endif #endif
#if TCG_TARGET_HAS_neg_i32 #if TCG_TARGET_HAS_neg_i32
case INDEX_op_neg_i32: case INDEX_op_neg_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, -t1); tci_write_reg(regs, t0, -t1);
break; break;
#endif #endif
@ -892,8 +878,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#endif #endif
case INDEX_op_extu_i32_i64: case INDEX_op_extu_i32_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, t1); tci_write_reg(regs, t0, (uint32_t)t1);
break; break;
#if TCG_TARGET_HAS_bswap16_i64 #if TCG_TARGET_HAS_bswap16_i64
case INDEX_op_bswap16_i64: case INDEX_op_bswap16_i64:
@ -905,7 +891,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#if TCG_TARGET_HAS_bswap32_i64 #if TCG_TARGET_HAS_bswap32_i64
case INDEX_op_bswap32_i64: case INDEX_op_bswap32_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r32(regs, &tb_ptr); t1 = tci_read_r(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap32(t1)); tci_write_reg(regs, t0, bswap32(t1));
break; break;
#endif #endif