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target/loongarch: Fix the meaning of ECFG reg's VS field

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By the manual of LoongArch CSR, the VS field(18:16 bits) of
ECFG reg means that the number of instructions between each
exception entry is 2^VS.

Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220701093407.2150607-9-yangxiaojuan@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Xiaojuan Yang 2022-07-01 17:34:04 +08:00 committed by Richard Henderson
parent 59e52dcff7
commit 4623367697
1 changed files with 4 additions and 0 deletions
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target/loongarch/cpu.c
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@ -223,6 +223,10 @@ static void loongarch_cpu_do_interrupt(CPUState *cs)
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0); env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0); env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
if (vec_size) {
vec_size = (1 << vec_size) * 4;
}
if (cs->exception_index == EXCCODE_INT) { if (cs->exception_index == EXCCODE_INT) {
/* Interrupt */ /* Interrupt */
uint32_t vector = 0; uint32_t vector = 0;