Various fixes related to frida mode (#445)
* Fix lint errors * Fix incorrect address for unfreed allocations when reseting * Use hash for edge ids * Fmt
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9f6872ac68
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1608294d0b
@ -292,13 +292,14 @@ impl Allocator {
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self.allocations
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self.allocations
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.insert(metadata.address + self.page_size, metadata);
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.insert(metadata.address + self.page_size, metadata);
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// println!("serving address: {:?}, size: {:x}", address, size);
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//println!("serving address: {:?}, size: {:x}", address, size);
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address
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address
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}
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}
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/// Releases the allocation at the given address.
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/// Releases the allocation at the given address.
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#[allow(clippy::missing_safety_doc)]
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#[allow(clippy::missing_safety_doc)]
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pub unsafe fn release(&mut self, ptr: *mut c_void) {
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pub unsafe fn release(&mut self, ptr: *mut c_void) {
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//println!("freeing address: {:?}", ptr);
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let mut metadata = if let Some(metadata) = self.allocations.get_mut(&(ptr as usize)) {
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let mut metadata = if let Some(metadata) = self.allocations.get_mut(&(ptr as usize)) {
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metadata
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metadata
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} else {
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} else {
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@ -379,7 +380,8 @@ impl Allocator {
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}
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}
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for allocation in tmp_allocations {
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for allocation in tmp_allocations {
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self.allocations.insert(allocation.address, allocation);
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self.allocations
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.insert(allocation.address + self.page_size, allocation);
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}
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}
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self.total_allocation_size = 0;
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self.total_allocation_size = 0;
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@ -1084,7 +1084,7 @@ impl AsanRuntime {
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{
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{
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index_reg -= capstone::arch::arm64::Arm64Reg::ARM64_REG_S0 as u16;
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index_reg -= capstone::arch::arm64::Arm64Reg::ARM64_REG_S0 as u16;
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}
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}
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fault_address += self.regs[index_reg as usize] as usize;
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fault_address += self.regs[index_reg as usize];
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}
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}
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let backtrace = Backtrace::new();
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let backtrace = Backtrace::new();
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@ -2086,6 +2086,7 @@ impl AsanRuntime {
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self.blob_check_mem_64bytes.as_ref().unwrap()
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self.blob_check_mem_64bytes.as_ref().unwrap()
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}
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}
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/// Determine if the instruction is 'interesting' for the purposes of ASAN
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#[cfg(target_arch = "aarch64")]
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#[cfg(target_arch = "aarch64")]
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#[inline]
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#[inline]
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pub fn asan_is_interesting_instruction(
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pub fn asan_is_interesting_instruction(
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@ -2359,6 +2360,7 @@ impl AsanRuntime {
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writer.put_lea_reg_reg_offset(X86Register::Rsp, X86Register::Rsp, redzone_size);
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writer.put_lea_reg_reg_offset(X86Register::Rsp, X86Register::Rsp, redzone_size);
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}
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}
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/// Emit a shadow memory check into the instruction stream
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#[cfg(target_arch = "aarch64")]
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#[cfg(target_arch = "aarch64")]
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#[inline]
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#[inline]
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pub fn emit_shadow_check(
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pub fn emit_shadow_check(
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@ -195,12 +195,7 @@ impl AsanErrors {
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.set_color(ColorSpec::new().set_fg(Some(Color::Yellow)))
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.set_color(ColorSpec::new().set_fg(Some(Color::Yellow)))
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.unwrap();
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.unwrap();
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}
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}
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write!(
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write!(output, "x{:02}: 0x{:016x} ", reg, error.registers[reg]).unwrap();
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output,
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"x{:02}: 0x{:016x} ",
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reg, error.registers[reg as usize]
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)
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.unwrap();
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output.reset().unwrap();
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output.reset().unwrap();
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if reg % 4 == 3 {
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if reg % 4 == 3 {
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writeln!(output).unwrap();
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writeln!(output).unwrap();
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@ -459,7 +454,7 @@ impl AsanErrors {
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.set_color(ColorSpec::new().set_fg(Some(Color::Yellow)))
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.set_color(ColorSpec::new().set_fg(Some(Color::Yellow)))
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.unwrap();
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.unwrap();
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}
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}
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write!(output, "x{:02}: 0x{:016x} ", reg, registers[reg as usize]).unwrap();
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write!(output, "x{:02}: 0x{:016x} ", reg, registers[reg]).unwrap();
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output.reset().unwrap();
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output.reset().unwrap();
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if reg % 4 == 3 {
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if reg % 4 == 3 {
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writeln!(output).unwrap();
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writeln!(output).unwrap();
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@ -127,6 +127,15 @@ impl CoverageRuntime {
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/// Emits coverage mapping into the current basic block.
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/// Emits coverage mapping into the current basic block.
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#[inline]
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#[inline]
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pub fn emit_coverage_mapping(&mut self, address: u64, output: &StalkerOutput) {
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pub fn emit_coverage_mapping(&mut self, address: u64, output: &StalkerOutput) {
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let tmp = (address >> 32) + ((address & 0xffffffff) << 32);
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let bitflip = 0x1cad21f72c81017c ^ 0xdb979082e96dd4de;
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let mut h64 = tmp ^ bitflip;
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h64 = h64.rotate_left(49) & h64.rotate_left(24);
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h64 *= 0x9FB21C651E98DF25;
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h64 ^= (h64 >> 35) + 8;
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h64 *= 0x9FB21C651E98DF25;
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h64 ^= h64 >> 28;
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let writer = output.writer();
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let writer = output.writer();
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#[allow(clippy::cast_possible_wrap)] // gum redzone size is u32, we need an offset as i32.
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#[allow(clippy::cast_possible_wrap)] // gum redzone size is u32, we need an offset as i32.
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let redzone_size = i64::from(frida_gum_sys::GUM_RED_ZONE_SIZE);
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let redzone_size = i64::from(frida_gum_sys::GUM_RED_ZONE_SIZE);
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@ -153,10 +162,7 @@ impl CoverageRuntime {
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{
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{
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writer.put_lea_reg_reg_offset(X86Register::Rsp, X86Register::Rsp, -(redzone_size));
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writer.put_lea_reg_reg_offset(X86Register::Rsp, X86Register::Rsp, -(redzone_size));
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writer.put_push_reg(X86Register::Rdi);
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writer.put_push_reg(X86Register::Rdi);
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writer.put_mov_reg_address(
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writer.put_mov_reg_address(X86Register::Rdi, h64 & (MAP_SIZE as u64 - 1));
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X86Register::Rdi,
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((address >> 4) ^ (address << 8)) & (MAP_SIZE - 1) as u64,
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);
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writer.put_call_address(self.current_log_impl);
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writer.put_call_address(self.current_log_impl);
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writer.put_pop_reg(X86Register::Rdi);
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writer.put_pop_reg(X86Register::Rdi);
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writer.put_lea_reg_reg_offset(X86Register::Rsp, X86Register::Rsp, redzone_size);
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writer.put_lea_reg_reg_offset(X86Register::Rsp, X86Register::Rsp, redzone_size);
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@ -167,19 +173,17 @@ impl CoverageRuntime {
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Aarch64Register::Lr,
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Aarch64Register::Lr,
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Aarch64Register::X0,
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Aarch64Register::X0,
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Aarch64Register::Sp,
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Aarch64Register::Sp,
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-(16 + redzone_size) as i64,
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-(16 + redzone_size),
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IndexMode::PreAdjust,
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IndexMode::PreAdjust,
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);
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);
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writer.put_ldr_reg_u64(
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writer.put_ldr_reg_u64(Aarch64Register::X0, h64 & (MAP_SIZE as u64 - 1));
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Aarch64Register::X0,
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((address >> 4) ^ (address << 8)) & (MAP_SIZE - 1) as u64,
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);
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writer.put_bl_imm(self.current_log_impl);
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writer.put_bl_imm(self.current_log_impl);
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writer.put_ldp_reg_reg_reg_offset(
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writer.put_ldp_reg_reg_reg_offset(
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Aarch64Register::Lr,
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Aarch64Register::Lr,
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Aarch64Register::X0,
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Aarch64Register::X0,
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Aarch64Register::Sp,
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Aarch64Register::Sp,
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16 + redzone_size as i64,
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16 + redzone_size,
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IndexMode::PostAdjust,
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IndexMode::PostAdjust,
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);
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);
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}
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}
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@ -285,7 +285,7 @@ impl<'a> FridaInstrumentationHelper<'a> {
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for instruction in basic_block {
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for instruction in basic_block {
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let instr = instruction.instr();
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let instr = instruction.instr();
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let address = instr.address();
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let address = instr.address();
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// println!("block @ {:x} transformed to {:x}", address, output.writer().pc());
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//println!("block @ {:x} transformed to {:x}", address, output.writer().pc());
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//println!(
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//println!(
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//"address: {:x} contains: {:?}",
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//"address: {:x} contains: {:?}",
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@ -297,7 +297,7 @@ impl<'a> FridaInstrumentationHelper<'a> {
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if helper.ranges.contains_key(&(address as usize)) {
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if helper.ranges.contains_key(&(address as usize)) {
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if first {
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if first {
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first = false;
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first = false;
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// println!("block @ {:x} transformed to {:x}", address, output.writer().pc());
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//println!("block @ {:x} transformed to {:x}", address, output.writer().pc());
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if helper.options().coverage_enabled() {
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if helper.options().coverage_enabled() {
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helper.coverage_rt.emit_coverage_mapping(address, &output);
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helper.coverage_rt.emit_coverage_mapping(address, &output);
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}
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}
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@ -399,6 +399,7 @@ impl<'a> FridaInstrumentationHelper<'a> {
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self.options
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self.options
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}
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}
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/// Determine the width of the specified instruction
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#[cfg(target_arch = "aarch64")]
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#[cfg(target_arch = "aarch64")]
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#[inline]
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#[inline]
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pub fn instruction_width(instr: &Insn, operands: &Vec<arch::ArchOperand>) -> u32 {
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pub fn instruction_width(instr: &Insn, operands: &Vec<arch::ArchOperand>) -> u32 {
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@ -465,6 +466,7 @@ impl<'a> FridaInstrumentationHelper<'a> {
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8 * num_registers
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8 * num_registers
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}
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}
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/// Convert from a capstone register id to a frida InstructionWriter register index
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#[cfg(target_arch = "aarch64")]
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#[cfg(target_arch = "aarch64")]
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#[inline]
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#[inline]
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pub fn writer_register(reg: capstone::RegId) -> Aarch64Register {
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pub fn writer_register(reg: capstone::RegId) -> Aarch64Register {
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