244 lines
7.5 KiB
C
244 lines
7.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
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* Author: James.Qian.Wang <james.qian.wang@arm.com>
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*
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*/
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#ifndef _KOMEDA_DEV_H_
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#define _KOMEDA_DEV_H_
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#include <linux/device.h>
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#include <linux/clk.h>
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#include "komeda_pipeline.h"
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#include "malidp_product.h"
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#include "komeda_format_caps.h"
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#define KOMEDA_EVENT_VSYNC BIT_ULL(0)
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#define KOMEDA_EVENT_FLIP BIT_ULL(1)
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#define KOMEDA_EVENT_URUN BIT_ULL(2)
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#define KOMEDA_EVENT_IBSY BIT_ULL(3)
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#define KOMEDA_EVENT_OVR BIT_ULL(4)
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#define KOMEDA_EVENT_EOW BIT_ULL(5)
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#define KOMEDA_EVENT_MODE BIT_ULL(6)
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#define KOMEDA_EVENT_FULL BIT_ULL(7)
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#define KOMEDA_EVENT_EMPTY BIT_ULL(8)
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#define KOMEDA_ERR_TETO BIT_ULL(14)
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#define KOMEDA_ERR_TEMR BIT_ULL(15)
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#define KOMEDA_ERR_TITR BIT_ULL(16)
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#define KOMEDA_ERR_CPE BIT_ULL(17)
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#define KOMEDA_ERR_CFGE BIT_ULL(18)
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#define KOMEDA_ERR_AXIE BIT_ULL(19)
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#define KOMEDA_ERR_ACE0 BIT_ULL(20)
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#define KOMEDA_ERR_ACE1 BIT_ULL(21)
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#define KOMEDA_ERR_ACE2 BIT_ULL(22)
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#define KOMEDA_ERR_ACE3 BIT_ULL(23)
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#define KOMEDA_ERR_DRIFTTO BIT_ULL(24)
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#define KOMEDA_ERR_FRAMETO BIT_ULL(25)
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#define KOMEDA_ERR_CSCE BIT_ULL(26)
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#define KOMEDA_ERR_ZME BIT_ULL(27)
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#define KOMEDA_ERR_MERR BIT_ULL(28)
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#define KOMEDA_ERR_TCF BIT_ULL(29)
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#define KOMEDA_ERR_TTNG BIT_ULL(30)
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#define KOMEDA_ERR_TTF BIT_ULL(31)
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#define KOMEDA_ERR_EVENTS \
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(KOMEDA_EVENT_URUN | KOMEDA_EVENT_IBSY | KOMEDA_EVENT_OVR |\
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KOMEDA_ERR_TETO | KOMEDA_ERR_TEMR | KOMEDA_ERR_TITR |\
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KOMEDA_ERR_CPE | KOMEDA_ERR_CFGE | KOMEDA_ERR_AXIE |\
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KOMEDA_ERR_ACE0 | KOMEDA_ERR_ACE1 | KOMEDA_ERR_ACE2 |\
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KOMEDA_ERR_ACE3 | KOMEDA_ERR_DRIFTTO | KOMEDA_ERR_FRAMETO |\
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KOMEDA_ERR_ZME | KOMEDA_ERR_MERR | KOMEDA_ERR_TCF |\
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KOMEDA_ERR_TTNG | KOMEDA_ERR_TTF)
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#define KOMEDA_WARN_EVENTS \
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(KOMEDA_ERR_CSCE | KOMEDA_EVENT_FULL | KOMEDA_EVENT_EMPTY)
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#define KOMEDA_INFO_EVENTS (0 \
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| KOMEDA_EVENT_VSYNC \
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| KOMEDA_EVENT_FLIP \
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| KOMEDA_EVENT_EOW \
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| KOMEDA_EVENT_MODE \
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)
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/* pipeline DT ports */
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enum {
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KOMEDA_OF_PORT_OUTPUT = 0,
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KOMEDA_OF_PORT_COPROC = 1,
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};
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struct komeda_chip_info {
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u32 arch_id;
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u32 core_id;
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u32 core_info;
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u32 bus_width;
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};
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struct komeda_dev;
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struct komeda_events {
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u64 global;
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u64 pipes[KOMEDA_MAX_PIPELINES];
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};
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/**
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* struct komeda_dev_funcs
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*
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* Supplied by chip level and returned by the chip entry function xxx_identify,
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*/
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struct komeda_dev_funcs {
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/**
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* @init_format_table:
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*
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* initialize &komeda_dev->format_table, this function should be called
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* before the &enum_resource
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*/
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void (*init_format_table)(struct komeda_dev *mdev);
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/**
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* @enum_resources:
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*
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* for CHIP to report or add pipeline and component resources to CORE
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*/
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int (*enum_resources)(struct komeda_dev *mdev);
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/** @cleanup: call to chip to cleanup komeda_dev->chip data */
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void (*cleanup)(struct komeda_dev *mdev);
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/** @connect_iommu: Optional, connect to external iommu */
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int (*connect_iommu)(struct komeda_dev *mdev);
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/** @disconnect_iommu: Optional, disconnect to external iommu */
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int (*disconnect_iommu)(struct komeda_dev *mdev);
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/**
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* @irq_handler:
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*
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* for CORE to get the HW event from the CHIP when interrupt happened.
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*/
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irqreturn_t (*irq_handler)(struct komeda_dev *mdev,
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struct komeda_events *events);
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/** @enable_irq: enable irq */
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int (*enable_irq)(struct komeda_dev *mdev);
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/** @disable_irq: disable irq */
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int (*disable_irq)(struct komeda_dev *mdev);
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/** @on_off_vblank: notify HW to on/off vblank */
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void (*on_off_vblank)(struct komeda_dev *mdev,
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int master_pipe, bool on);
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/** @dump_register: Optional, dump registers to seq_file */
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void (*dump_register)(struct komeda_dev *mdev, struct seq_file *seq);
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/**
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* @change_opmode:
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*
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* Notify HW to switch to a new display operation mode.
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*/
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int (*change_opmode)(struct komeda_dev *mdev, int new_mode);
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/** @flush: Notify the HW to flush or kickoff the update */
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void (*flush)(struct komeda_dev *mdev,
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int master_pipe, u32 active_pipes);
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};
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/*
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* DISPLAY_MODE describes how many display been enabled, and which will be
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* passed to CHIP by &komeda_dev_funcs->change_opmode(), then CHIP can do the
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* pipeline resources assignment according to this usage hint.
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* - KOMEDA_MODE_DISP0: Only one display enabled, pipeline-0 work as master.
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* - KOMEDA_MODE_DISP1: Only one display enabled, pipeline-0 work as master.
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* - KOMEDA_MODE_DUAL_DISP: Dual display mode, both display has been enabled.
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* And D71 supports assign two pipelines to one single display on mode
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* KOMEDA_MODE_DISP0/DISP1
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*/
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enum {
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KOMEDA_MODE_INACTIVE = 0,
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KOMEDA_MODE_DISP0 = BIT(0),
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KOMEDA_MODE_DISP1 = BIT(1),
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KOMEDA_MODE_DUAL_DISP = KOMEDA_MODE_DISP0 | KOMEDA_MODE_DISP1,
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};
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/**
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* struct komeda_dev
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*
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* Pipeline and component are used to describe how to handle the pixel data.
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* komeda_device is for describing the whole view of the device, and the
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* control-abilites of device.
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*/
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struct komeda_dev {
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/** @dev: the base device structure */
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struct device *dev;
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/** @reg_base: the base address of komeda io space */
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u32 __iomem *reg_base;
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/** @chip: the basic chip information */
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struct komeda_chip_info chip;
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/** @fmt_tbl: initialized by &komeda_dev_funcs->init_format_table */
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struct komeda_format_caps_table fmt_tbl;
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/** @aclk: HW main engine clk */
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struct clk *aclk;
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/** @irq: irq number */
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int irq;
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/** @lock: used to protect dpmode */
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struct mutex lock;
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/** @dpmode: current display mode */
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u32 dpmode;
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/** @n_pipelines: the number of pipe in @pipelines */
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int n_pipelines;
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/** @pipelines: the komeda pipelines */
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struct komeda_pipeline *pipelines[KOMEDA_MAX_PIPELINES];
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/** @funcs: chip funcs to access to HW */
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const struct komeda_dev_funcs *funcs;
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/**
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* @chip_data:
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*
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* chip data will be added by &komeda_dev_funcs.enum_resources() and
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* destroyed by &komeda_dev_funcs.cleanup()
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*/
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void *chip_data;
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/** @iommu: iommu domain */
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struct iommu_domain *iommu;
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/** @debugfs_root: root directory of komeda debugfs */
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struct dentry *debugfs_root;
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/**
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* @err_verbosity: bitmask for how much extra info to print on error
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*
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* See KOMEDA_DEV_* macros for details. Low byte contains the debug
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* level categories, the high byte contains extra debug options.
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*/
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u16 err_verbosity;
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/* Print a single line per error per frame with error events. */
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#define KOMEDA_DEV_PRINT_ERR_EVENTS BIT(0)
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/* Print a single line per warning per frame with error events. */
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#define KOMEDA_DEV_PRINT_WARN_EVENTS BIT(1)
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/* Print a single line per info event per frame with error events. */
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#define KOMEDA_DEV_PRINT_INFO_EVENTS BIT(2)
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/* Dump DRM state on an error or warning event. */
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#define KOMEDA_DEV_PRINT_DUMP_STATE_ON_EVENT BIT(8)
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/* Disable rate limiting of event prints (normally one per commit) */
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#define KOMEDA_DEV_PRINT_DISABLE_RATELIMIT BIT(12)
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};
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static inline bool
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komeda_product_match(struct komeda_dev *mdev, u32 target)
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{
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return MALIDP_CORE_ID_PRODUCT_ID(mdev->chip.core_id) == target;
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}
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typedef const struct komeda_dev_funcs *
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(*komeda_identify_func)(u32 __iomem *reg, struct komeda_chip_info *chip);
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const struct komeda_dev_funcs *
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d71_identify(u32 __iomem *reg, struct komeda_chip_info *chip);
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struct komeda_dev *komeda_dev_create(struct device *dev);
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void komeda_dev_destroy(struct komeda_dev *mdev);
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struct komeda_dev *dev_to_mdev(struct device *dev);
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void komeda_print_events(struct komeda_events *evts, struct drm_device *dev);
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int komeda_dev_resume(struct komeda_dev *mdev);
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int komeda_dev_suspend(struct komeda_dev *mdev);
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#endif /*_KOMEDA_DEV_H_*/
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