1055 lines
26 KiB
C
1055 lines
26 KiB
C
/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#define SWSMU_CODE_LAYER_L4
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#include "amdgpu.h"
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#include "amdgpu_smu.h"
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#include "smu_cmn.h"
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#include "soc15_common.h"
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/*
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* DO NOT use these for err/warn/info/debug messages.
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* Use dev_err, dev_warn, dev_info and dev_dbg instead.
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* They are more MGPU friendly.
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*/
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#undef pr_err
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#undef pr_warn
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#undef pr_info
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#undef pr_debug
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#define MP1_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL
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#undef __SMU_DUMMY_MAP
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#define __SMU_DUMMY_MAP(type) #type
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static const char * const __smu_message_names[] = {
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SMU_MESSAGE_TYPES
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};
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#define smu_cmn_call_asic_func(intf, smu, args...) \
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((smu)->ppt_funcs ? ((smu)->ppt_funcs->intf ? \
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(smu)->ppt_funcs->intf(smu, ##args) : \
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-ENOTSUPP) : \
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-EINVAL)
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static const char *smu_get_message_name(struct smu_context *smu,
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enum smu_message_type type)
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{
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if (type < 0 || type >= SMU_MSG_MAX_COUNT)
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return "unknown smu message";
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return __smu_message_names[type];
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}
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static void smu_cmn_read_arg(struct smu_context *smu,
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uint32_t *arg)
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{
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struct amdgpu_device *adev = smu->adev;
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*arg = RREG32(smu->param_reg);
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}
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/* Redefine the SMU error codes here.
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*
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* Note that these definitions are redundant and should be removed
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* when the SMU has exported a unified header file containing these
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* macros, which header file we can just include and use the SMU's
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* macros. At the moment, these error codes are defined by the SMU
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* per-ASIC unfortunately, yet we're a one driver for all ASICs.
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*/
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#define SMU_RESP_NONE 0
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#define SMU_RESP_OK 1
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#define SMU_RESP_CMD_FAIL 0xFF
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#define SMU_RESP_CMD_UNKNOWN 0xFE
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#define SMU_RESP_CMD_BAD_PREREQ 0xFD
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#define SMU_RESP_BUSY_OTHER 0xFC
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#define SMU_RESP_DEBUG_END 0xFB
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/**
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* __smu_cmn_poll_stat -- poll for a status from the SMU
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* @smu: a pointer to SMU context
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*
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* Returns the status of the SMU, which could be,
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* 0, the SMU is busy with your command;
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* 1, execution status: success, execution result: success;
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* 0xFF, execution status: success, execution result: failure;
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* 0xFE, unknown command;
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* 0xFD, valid command, but bad (command) prerequisites;
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* 0xFC, the command was rejected as the SMU is busy;
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* 0xFB, "SMC_Result_DebugDataDumpEnd".
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*
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* The values here are not defined by macros, because I'd rather we
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* include a single header file which defines them, which is
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* maintained by the SMU FW team, so that we're impervious to firmware
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* changes. At the moment those values are defined in various header
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* files, one for each ASIC, yet here we're a single ASIC-agnostic
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* interface. Such a change can be followed-up by a subsequent patch.
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*/
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static u32 __smu_cmn_poll_stat(struct smu_context *smu)
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{
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struct amdgpu_device *adev = smu->adev;
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int timeout = adev->usec_timeout * 20;
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u32 reg;
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for ( ; timeout > 0; timeout--) {
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reg = RREG32(smu->resp_reg);
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if ((reg & MP1_C2PMSG_90__CONTENT_MASK) != 0)
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break;
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udelay(1);
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}
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return reg;
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}
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static void __smu_cmn_reg_print_error(struct smu_context *smu,
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u32 reg_c2pmsg_90,
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int msg_index,
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u32 param,
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enum smu_message_type msg)
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{
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struct amdgpu_device *adev = smu->adev;
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const char *message = smu_get_message_name(smu, msg);
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u32 msg_idx, prm;
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switch (reg_c2pmsg_90) {
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case SMU_RESP_NONE: {
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msg_idx = RREG32(smu->msg_reg);
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prm = RREG32(smu->param_reg);
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dev_err_ratelimited(adev->dev,
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"SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x%08X SMN_C2PMSG_82:0x%08X",
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msg_idx, prm);
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}
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break;
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case SMU_RESP_OK:
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/* The SMU executed the command. It completed with a
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* successful result.
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*/
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break;
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case SMU_RESP_CMD_FAIL:
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/* The SMU executed the command. It completed with an
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* unsuccessful result.
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*/
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break;
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case SMU_RESP_CMD_UNKNOWN:
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dev_err_ratelimited(adev->dev,
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"SMU: unknown command: index:%d param:0x%08X message:%s",
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msg_index, param, message);
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break;
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case SMU_RESP_CMD_BAD_PREREQ:
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dev_err_ratelimited(adev->dev,
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"SMU: valid command, bad prerequisites: index:%d param:0x%08X message:%s",
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msg_index, param, message);
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break;
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case SMU_RESP_BUSY_OTHER:
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dev_err_ratelimited(adev->dev,
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"SMU: I'm very busy for your command: index:%d param:0x%08X message:%s",
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msg_index, param, message);
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break;
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case SMU_RESP_DEBUG_END:
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dev_err_ratelimited(adev->dev,
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"SMU: I'm debugging!");
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break;
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default:
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dev_err_ratelimited(adev->dev,
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"SMU: response:0x%08X for index:%d param:0x%08X message:%s?",
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reg_c2pmsg_90, msg_index, param, message);
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break;
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}
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}
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static int __smu_cmn_reg2errno(struct smu_context *smu, u32 reg_c2pmsg_90)
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{
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int res;
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switch (reg_c2pmsg_90) {
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case SMU_RESP_NONE:
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/* The SMU is busy--still executing your command.
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*/
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res = -ETIME;
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break;
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case SMU_RESP_OK:
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res = 0;
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break;
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case SMU_RESP_CMD_FAIL:
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/* Command completed successfully, but the command
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* status was failure.
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*/
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res = -EIO;
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break;
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case SMU_RESP_CMD_UNKNOWN:
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/* Unknown command--ignored by the SMU.
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*/
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res = -EOPNOTSUPP;
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break;
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case SMU_RESP_CMD_BAD_PREREQ:
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/* Valid command--bad prerequisites.
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*/
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res = -EINVAL;
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break;
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case SMU_RESP_BUSY_OTHER:
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/* The SMU is busy with other commands. The client
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* should retry in 10 us.
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*/
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res = -EBUSY;
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break;
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default:
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/* Unknown or debug response from the SMU.
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*/
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res = -EREMOTEIO;
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break;
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}
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return res;
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}
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static void __smu_cmn_send_msg(struct smu_context *smu,
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u16 msg,
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u32 param)
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{
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struct amdgpu_device *adev = smu->adev;
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WREG32(smu->resp_reg, 0);
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WREG32(smu->param_reg, param);
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WREG32(smu->msg_reg, msg);
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}
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static int __smu_cmn_send_debug_msg(struct smu_context *smu,
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u32 msg,
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u32 param)
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{
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struct amdgpu_device *adev = smu->adev;
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WREG32(smu->debug_param_reg, param);
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WREG32(smu->debug_msg_reg, msg);
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WREG32(smu->debug_resp_reg, 0);
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return 0;
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}
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/**
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* smu_cmn_send_msg_without_waiting -- send the message; don't wait for status
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* @smu: pointer to an SMU context
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* @msg_index: message index
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* @param: message parameter to send to the SMU
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*
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* Send a message to the SMU with the parameter passed. Do not wait
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* for status/result of the message, thus the "without_waiting".
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*
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* Return 0 on success, -errno on error if we weren't able to _send_
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* the message for some reason. See __smu_cmn_reg2errno() for details
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* of the -errno.
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*/
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int smu_cmn_send_msg_without_waiting(struct smu_context *smu,
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uint16_t msg_index,
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uint32_t param)
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{
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struct amdgpu_device *adev = smu->adev;
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u32 reg;
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int res;
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if (adev->no_hw_access)
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return 0;
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reg = __smu_cmn_poll_stat(smu);
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res = __smu_cmn_reg2errno(smu, reg);
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if (reg == SMU_RESP_NONE ||
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res == -EREMOTEIO)
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goto Out;
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__smu_cmn_send_msg(smu, msg_index, param);
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res = 0;
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Out:
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if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) &&
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res && (res != -ETIME)) {
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amdgpu_device_halt(adev);
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WARN_ON(1);
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}
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return res;
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}
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/**
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* smu_cmn_wait_for_response -- wait for response from the SMU
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* @smu: pointer to an SMU context
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*
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* Wait for status from the SMU.
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*
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* Return 0 on success, -errno on error, indicating the execution
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* status and result of the message being waited for. See
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* __smu_cmn_reg2errno() for details of the -errno.
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*/
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int smu_cmn_wait_for_response(struct smu_context *smu)
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{
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u32 reg;
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int res;
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reg = __smu_cmn_poll_stat(smu);
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res = __smu_cmn_reg2errno(smu, reg);
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if (unlikely(smu->adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) &&
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res && (res != -ETIME)) {
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amdgpu_device_halt(smu->adev);
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WARN_ON(1);
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}
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return res;
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}
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/**
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* smu_cmn_send_smc_msg_with_param -- send a message with parameter
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* @smu: pointer to an SMU context
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* @msg: message to send
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* @param: parameter to send to the SMU
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* @read_arg: pointer to u32 to return a value from the SMU back
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* to the caller
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*
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* Send the message @msg with parameter @param to the SMU, wait for
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* completion of the command, and return back a value from the SMU in
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* @read_arg pointer.
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*
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* Return 0 on success, -errno when a problem is encountered sending
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* message or receiving reply. If there is a PCI bus recovery or
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* the destination is a virtual GPU which does not allow this message
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* type, the message is simply dropped and success is also returned.
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* See __smu_cmn_reg2errno() for details of the -errno.
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*
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* If we weren't able to send the message to the SMU, we also print
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* the error to the standard log.
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*
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* Command completion status is printed only if the -errno is
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* -EREMOTEIO, indicating that the SMU returned back an
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* undefined/unknown/unspecified result. All other cases are
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* well-defined, not printed, but instead given back to the client to
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* decide what further to do.
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*
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* The return value, @read_arg is read back regardless, to give back
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* more information to the client, which on error would most likely be
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* @param, but we can't assume that. This also eliminates more
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* conditionals.
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*/
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int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
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enum smu_message_type msg,
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uint32_t param,
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uint32_t *read_arg)
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{
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struct amdgpu_device *adev = smu->adev;
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int res, index;
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u32 reg;
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if (adev->no_hw_access)
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return 0;
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index = smu_cmn_to_asic_specific_index(smu,
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CMN2ASIC_MAPPING_MSG,
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msg);
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if (index < 0)
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return index == -EACCES ? 0 : index;
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mutex_lock(&smu->message_lock);
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reg = __smu_cmn_poll_stat(smu);
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res = __smu_cmn_reg2errno(smu, reg);
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if (reg == SMU_RESP_NONE ||
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res == -EREMOTEIO) {
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__smu_cmn_reg_print_error(smu, reg, index, param, msg);
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goto Out;
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}
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__smu_cmn_send_msg(smu, (uint16_t) index, param);
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reg = __smu_cmn_poll_stat(smu);
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res = __smu_cmn_reg2errno(smu, reg);
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if (res != 0)
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__smu_cmn_reg_print_error(smu, reg, index, param, msg);
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if (read_arg)
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smu_cmn_read_arg(smu, read_arg);
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Out:
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if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) && res) {
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amdgpu_device_halt(adev);
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WARN_ON(1);
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}
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mutex_unlock(&smu->message_lock);
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return res;
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}
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int smu_cmn_send_smc_msg(struct smu_context *smu,
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enum smu_message_type msg,
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uint32_t *read_arg)
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{
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return smu_cmn_send_smc_msg_with_param(smu,
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msg,
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0,
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read_arg);
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}
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int smu_cmn_send_debug_smc_msg(struct smu_context *smu,
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uint32_t msg)
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{
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return __smu_cmn_send_debug_msg(smu, msg, 0);
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}
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|
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int smu_cmn_to_asic_specific_index(struct smu_context *smu,
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enum smu_cmn2asic_mapping_type type,
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uint32_t index)
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{
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struct cmn2asic_msg_mapping msg_mapping;
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struct cmn2asic_mapping mapping;
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switch (type) {
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case CMN2ASIC_MAPPING_MSG:
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if (index >= SMU_MSG_MAX_COUNT ||
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!smu->message_map)
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return -EINVAL;
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msg_mapping = smu->message_map[index];
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if (!msg_mapping.valid_mapping)
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return -EINVAL;
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|
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if (amdgpu_sriov_vf(smu->adev) &&
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!msg_mapping.valid_in_vf)
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return -EACCES;
|
|
|
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return msg_mapping.map_to;
|
|
|
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case CMN2ASIC_MAPPING_CLK:
|
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if (index >= SMU_CLK_COUNT ||
|
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!smu->clock_map)
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return -EINVAL;
|
|
|
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mapping = smu->clock_map[index];
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if (!mapping.valid_mapping)
|
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return -EINVAL;
|
|
|
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return mapping.map_to;
|
|
|
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case CMN2ASIC_MAPPING_FEATURE:
|
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if (index >= SMU_FEATURE_COUNT ||
|
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!smu->feature_map)
|
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return -EINVAL;
|
|
|
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mapping = smu->feature_map[index];
|
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if (!mapping.valid_mapping)
|
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return -EINVAL;
|
|
|
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return mapping.map_to;
|
|
|
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case CMN2ASIC_MAPPING_TABLE:
|
|
if (index >= SMU_TABLE_COUNT ||
|
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!smu->table_map)
|
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return -EINVAL;
|
|
|
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mapping = smu->table_map[index];
|
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if (!mapping.valid_mapping)
|
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return -EINVAL;
|
|
|
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return mapping.map_to;
|
|
|
|
case CMN2ASIC_MAPPING_PWR:
|
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if (index >= SMU_POWER_SOURCE_COUNT ||
|
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!smu->pwr_src_map)
|
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return -EINVAL;
|
|
|
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mapping = smu->pwr_src_map[index];
|
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if (!mapping.valid_mapping)
|
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return -EINVAL;
|
|
|
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return mapping.map_to;
|
|
|
|
case CMN2ASIC_MAPPING_WORKLOAD:
|
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if (index > PP_SMC_POWER_PROFILE_WINDOW3D ||
|
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!smu->workload_map)
|
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return -EINVAL;
|
|
|
|
mapping = smu->workload_map[index];
|
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if (!mapping.valid_mapping)
|
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return -EINVAL;
|
|
|
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return mapping.map_to;
|
|
|
|
default:
|
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return -EINVAL;
|
|
}
|
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}
|
|
|
|
int smu_cmn_feature_is_supported(struct smu_context *smu,
|
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enum smu_feature_mask mask)
|
|
{
|
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struct smu_feature *feature = &smu->smu_feature;
|
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int feature_id;
|
|
|
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feature_id = smu_cmn_to_asic_specific_index(smu,
|
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CMN2ASIC_MAPPING_FEATURE,
|
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mask);
|
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if (feature_id < 0)
|
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return 0;
|
|
|
|
WARN_ON(feature_id > feature->feature_num);
|
|
|
|
return test_bit(feature_id, feature->supported);
|
|
}
|
|
|
|
static int __smu_get_enabled_features(struct smu_context *smu,
|
|
uint64_t *enabled_features)
|
|
{
|
|
return smu_cmn_call_asic_func(get_enabled_mask, smu, enabled_features);
|
|
}
|
|
|
|
int smu_cmn_feature_is_enabled(struct smu_context *smu,
|
|
enum smu_feature_mask mask)
|
|
{
|
|
struct amdgpu_device *adev = smu->adev;
|
|
uint64_t enabled_features;
|
|
int feature_id;
|
|
|
|
if (__smu_get_enabled_features(smu, &enabled_features)) {
|
|
dev_err(adev->dev, "Failed to retrieve enabled ppfeatures!\n");
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* For Renoir and Cyan Skillfish, they are assumed to have all features
|
|
* enabled. Also considering they have no feature_map available, the
|
|
* check here can avoid unwanted feature_map check below.
|
|
*/
|
|
if (enabled_features == ULLONG_MAX)
|
|
return 1;
|
|
|
|
feature_id = smu_cmn_to_asic_specific_index(smu,
|
|
CMN2ASIC_MAPPING_FEATURE,
|
|
mask);
|
|
if (feature_id < 0)
|
|
return 0;
|
|
|
|
return test_bit(feature_id, (unsigned long *)&enabled_features);
|
|
}
|
|
|
|
bool smu_cmn_clk_dpm_is_enabled(struct smu_context *smu,
|
|
enum smu_clk_type clk_type)
|
|
{
|
|
enum smu_feature_mask feature_id = 0;
|
|
|
|
switch (clk_type) {
|
|
case SMU_MCLK:
|
|
case SMU_UCLK:
|
|
feature_id = SMU_FEATURE_DPM_UCLK_BIT;
|
|
break;
|
|
case SMU_GFXCLK:
|
|
case SMU_SCLK:
|
|
feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
|
|
break;
|
|
case SMU_SOCCLK:
|
|
feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
|
|
break;
|
|
case SMU_VCLK:
|
|
case SMU_VCLK1:
|
|
feature_id = SMU_FEATURE_DPM_VCLK_BIT;
|
|
break;
|
|
case SMU_DCLK:
|
|
case SMU_DCLK1:
|
|
feature_id = SMU_FEATURE_DPM_DCLK_BIT;
|
|
break;
|
|
case SMU_FCLK:
|
|
feature_id = SMU_FEATURE_DPM_FCLK_BIT;
|
|
break;
|
|
default:
|
|
return true;
|
|
}
|
|
|
|
if (!smu_cmn_feature_is_enabled(smu, feature_id))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
int smu_cmn_get_enabled_mask(struct smu_context *smu,
|
|
uint64_t *feature_mask)
|
|
{
|
|
uint32_t *feature_mask_high;
|
|
uint32_t *feature_mask_low;
|
|
int ret = 0, index = 0;
|
|
|
|
if (!feature_mask)
|
|
return -EINVAL;
|
|
|
|
feature_mask_low = &((uint32_t *)feature_mask)[0];
|
|
feature_mask_high = &((uint32_t *)feature_mask)[1];
|
|
|
|
index = smu_cmn_to_asic_specific_index(smu,
|
|
CMN2ASIC_MAPPING_MSG,
|
|
SMU_MSG_GetEnabledSmuFeatures);
|
|
if (index > 0) {
|
|
ret = smu_cmn_send_smc_msg_with_param(smu,
|
|
SMU_MSG_GetEnabledSmuFeatures,
|
|
0,
|
|
feature_mask_low);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = smu_cmn_send_smc_msg_with_param(smu,
|
|
SMU_MSG_GetEnabledSmuFeatures,
|
|
1,
|
|
feature_mask_high);
|
|
} else {
|
|
ret = smu_cmn_send_smc_msg(smu,
|
|
SMU_MSG_GetEnabledSmuFeaturesHigh,
|
|
feature_mask_high);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = smu_cmn_send_smc_msg(smu,
|
|
SMU_MSG_GetEnabledSmuFeaturesLow,
|
|
feature_mask_low);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
uint64_t smu_cmn_get_indep_throttler_status(
|
|
const unsigned long dep_status,
|
|
const uint8_t *throttler_map)
|
|
{
|
|
uint64_t indep_status = 0;
|
|
uint8_t dep_bit = 0;
|
|
|
|
for_each_set_bit(dep_bit, &dep_status, 32)
|
|
indep_status |= 1ULL << throttler_map[dep_bit];
|
|
|
|
return indep_status;
|
|
}
|
|
|
|
int smu_cmn_feature_update_enable_state(struct smu_context *smu,
|
|
uint64_t feature_mask,
|
|
bool enabled)
|
|
{
|
|
int ret = 0;
|
|
|
|
if (enabled) {
|
|
ret = smu_cmn_send_smc_msg_with_param(smu,
|
|
SMU_MSG_EnableSmuFeaturesLow,
|
|
lower_32_bits(feature_mask),
|
|
NULL);
|
|
if (ret)
|
|
return ret;
|
|
ret = smu_cmn_send_smc_msg_with_param(smu,
|
|
SMU_MSG_EnableSmuFeaturesHigh,
|
|
upper_32_bits(feature_mask),
|
|
NULL);
|
|
} else {
|
|
ret = smu_cmn_send_smc_msg_with_param(smu,
|
|
SMU_MSG_DisableSmuFeaturesLow,
|
|
lower_32_bits(feature_mask),
|
|
NULL);
|
|
if (ret)
|
|
return ret;
|
|
ret = smu_cmn_send_smc_msg_with_param(smu,
|
|
SMU_MSG_DisableSmuFeaturesHigh,
|
|
upper_32_bits(feature_mask),
|
|
NULL);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int smu_cmn_feature_set_enabled(struct smu_context *smu,
|
|
enum smu_feature_mask mask,
|
|
bool enable)
|
|
{
|
|
int feature_id;
|
|
|
|
feature_id = smu_cmn_to_asic_specific_index(smu,
|
|
CMN2ASIC_MAPPING_FEATURE,
|
|
mask);
|
|
if (feature_id < 0)
|
|
return -EINVAL;
|
|
|
|
return smu_cmn_feature_update_enable_state(smu,
|
|
1ULL << feature_id,
|
|
enable);
|
|
}
|
|
|
|
#undef __SMU_DUMMY_MAP
|
|
#define __SMU_DUMMY_MAP(fea) #fea
|
|
static const char* __smu_feature_names[] = {
|
|
SMU_FEATURE_MASKS
|
|
};
|
|
|
|
static const char *smu_get_feature_name(struct smu_context *smu,
|
|
enum smu_feature_mask feature)
|
|
{
|
|
if (feature < 0 || feature >= SMU_FEATURE_COUNT)
|
|
return "unknown smu feature";
|
|
return __smu_feature_names[feature];
|
|
}
|
|
|
|
size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
|
|
char *buf)
|
|
{
|
|
int8_t sort_feature[max(SMU_FEATURE_COUNT, SMU_FEATURE_MAX)];
|
|
uint64_t feature_mask;
|
|
int i, feature_index;
|
|
uint32_t count = 0;
|
|
size_t size = 0;
|
|
|
|
if (__smu_get_enabled_features(smu, &feature_mask))
|
|
return 0;
|
|
|
|
size = sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n",
|
|
upper_32_bits(feature_mask), lower_32_bits(feature_mask));
|
|
|
|
memset(sort_feature, -1, sizeof(sort_feature));
|
|
|
|
for (i = 0; i < SMU_FEATURE_COUNT; i++) {
|
|
feature_index = smu_cmn_to_asic_specific_index(smu,
|
|
CMN2ASIC_MAPPING_FEATURE,
|
|
i);
|
|
if (feature_index < 0)
|
|
continue;
|
|
|
|
sort_feature[feature_index] = i;
|
|
}
|
|
|
|
size += sysfs_emit_at(buf, size, "%-2s. %-20s %-3s : %-s\n",
|
|
"No", "Feature", "Bit", "State");
|
|
|
|
for (feature_index = 0; feature_index < SMU_FEATURE_MAX; feature_index++) {
|
|
if (sort_feature[feature_index] < 0)
|
|
continue;
|
|
|
|
size += sysfs_emit_at(buf, size, "%02d. %-20s (%2d) : %s\n",
|
|
count++,
|
|
smu_get_feature_name(smu, sort_feature[feature_index]),
|
|
feature_index,
|
|
!!test_bit(feature_index, (unsigned long *)&feature_mask) ?
|
|
"enabled" : "disabled");
|
|
}
|
|
|
|
return size;
|
|
}
|
|
|
|
int smu_cmn_set_pp_feature_mask(struct smu_context *smu,
|
|
uint64_t new_mask)
|
|
{
|
|
int ret = 0;
|
|
uint64_t feature_mask;
|
|
uint64_t feature_2_enabled = 0;
|
|
uint64_t feature_2_disabled = 0;
|
|
|
|
ret = __smu_get_enabled_features(smu, &feature_mask);
|
|
if (ret)
|
|
return ret;
|
|
|
|
feature_2_enabled = ~feature_mask & new_mask;
|
|
feature_2_disabled = feature_mask & ~new_mask;
|
|
|
|
if (feature_2_enabled) {
|
|
ret = smu_cmn_feature_update_enable_state(smu,
|
|
feature_2_enabled,
|
|
true);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
if (feature_2_disabled) {
|
|
ret = smu_cmn_feature_update_enable_state(smu,
|
|
feature_2_disabled,
|
|
false);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* smu_cmn_disable_all_features_with_exception - disable all dpm features
|
|
* except this specified by
|
|
* @mask
|
|
*
|
|
* @smu: smu_context pointer
|
|
* @mask: the dpm feature which should not be disabled
|
|
* SMU_FEATURE_COUNT: no exception, all dpm features
|
|
* to disable
|
|
*
|
|
* Returns:
|
|
* 0 on success or a negative error code on failure.
|
|
*/
|
|
int smu_cmn_disable_all_features_with_exception(struct smu_context *smu,
|
|
enum smu_feature_mask mask)
|
|
{
|
|
uint64_t features_to_disable = U64_MAX;
|
|
int skipped_feature_id;
|
|
|
|
if (mask != SMU_FEATURE_COUNT) {
|
|
skipped_feature_id = smu_cmn_to_asic_specific_index(smu,
|
|
CMN2ASIC_MAPPING_FEATURE,
|
|
mask);
|
|
if (skipped_feature_id < 0)
|
|
return -EINVAL;
|
|
|
|
features_to_disable &= ~(1ULL << skipped_feature_id);
|
|
}
|
|
|
|
return smu_cmn_feature_update_enable_state(smu,
|
|
features_to_disable,
|
|
0);
|
|
}
|
|
|
|
int smu_cmn_get_smc_version(struct smu_context *smu,
|
|
uint32_t *if_version,
|
|
uint32_t *smu_version)
|
|
{
|
|
int ret = 0;
|
|
|
|
if (!if_version && !smu_version)
|
|
return -EINVAL;
|
|
|
|
if (smu->smc_fw_if_version && smu->smc_fw_version)
|
|
{
|
|
if (if_version)
|
|
*if_version = smu->smc_fw_if_version;
|
|
|
|
if (smu_version)
|
|
*smu_version = smu->smc_fw_version;
|
|
|
|
return 0;
|
|
}
|
|
|
|
if (if_version) {
|
|
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetDriverIfVersion, if_version);
|
|
if (ret)
|
|
return ret;
|
|
|
|
smu->smc_fw_if_version = *if_version;
|
|
}
|
|
|
|
if (smu_version) {
|
|
ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSmuVersion, smu_version);
|
|
if (ret)
|
|
return ret;
|
|
|
|
smu->smc_fw_version = *smu_version;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int smu_cmn_update_table(struct smu_context *smu,
|
|
enum smu_table_id table_index,
|
|
int argument,
|
|
void *table_data,
|
|
bool drv2smu)
|
|
{
|
|
struct smu_table_context *smu_table = &smu->smu_table;
|
|
struct amdgpu_device *adev = smu->adev;
|
|
struct smu_table *table = &smu_table->driver_table;
|
|
int table_id = smu_cmn_to_asic_specific_index(smu,
|
|
CMN2ASIC_MAPPING_TABLE,
|
|
table_index);
|
|
uint32_t table_size;
|
|
int ret = 0;
|
|
if (!table_data || table_id >= SMU_TABLE_COUNT || table_id < 0)
|
|
return -EINVAL;
|
|
|
|
table_size = smu_table->tables[table_index].size;
|
|
|
|
if (drv2smu) {
|
|
memcpy(table->cpu_addr, table_data, table_size);
|
|
/*
|
|
* Flush hdp cache: to guard the content seen by
|
|
* GPU is consitent with CPU.
|
|
*/
|
|
amdgpu_asic_flush_hdp(adev, NULL);
|
|
}
|
|
|
|
ret = smu_cmn_send_smc_msg_with_param(smu, drv2smu ?
|
|
SMU_MSG_TransferTableDram2Smu :
|
|
SMU_MSG_TransferTableSmu2Dram,
|
|
table_id | ((argument & 0xFFFF) << 16),
|
|
NULL);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!drv2smu) {
|
|
amdgpu_asic_invalidate_hdp(adev, NULL);
|
|
memcpy(table_data, table->cpu_addr, table_size);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int smu_cmn_write_watermarks_table(struct smu_context *smu)
|
|
{
|
|
void *watermarks_table = smu->smu_table.watermarks_table;
|
|
|
|
if (!watermarks_table)
|
|
return -EINVAL;
|
|
|
|
return smu_cmn_update_table(smu,
|
|
SMU_TABLE_WATERMARKS,
|
|
0,
|
|
watermarks_table,
|
|
true);
|
|
}
|
|
|
|
int smu_cmn_write_pptable(struct smu_context *smu)
|
|
{
|
|
void *pptable = smu->smu_table.driver_pptable;
|
|
|
|
return smu_cmn_update_table(smu,
|
|
SMU_TABLE_PPTABLE,
|
|
0,
|
|
pptable,
|
|
true);
|
|
}
|
|
|
|
int smu_cmn_get_metrics_table(struct smu_context *smu,
|
|
void *metrics_table,
|
|
bool bypass_cache)
|
|
{
|
|
struct smu_table_context *smu_table= &smu->smu_table;
|
|
uint32_t table_size =
|
|
smu_table->tables[SMU_TABLE_SMU_METRICS].size;
|
|
int ret = 0;
|
|
|
|
if (bypass_cache ||
|
|
!smu_table->metrics_time ||
|
|
time_after(jiffies, smu_table->metrics_time + msecs_to_jiffies(1))) {
|
|
ret = smu_cmn_update_table(smu,
|
|
SMU_TABLE_SMU_METRICS,
|
|
0,
|
|
smu_table->metrics_table,
|
|
false);
|
|
if (ret) {
|
|
dev_info(smu->adev->dev, "Failed to export SMU metrics table!\n");
|
|
return ret;
|
|
}
|
|
smu_table->metrics_time = jiffies;
|
|
}
|
|
|
|
if (metrics_table)
|
|
memcpy(metrics_table, smu_table->metrics_table, table_size);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int smu_cmn_get_combo_pptable(struct smu_context *smu)
|
|
{
|
|
void *pptable = smu->smu_table.combo_pptable;
|
|
|
|
return smu_cmn_update_table(smu,
|
|
SMU_TABLE_COMBO_PPTABLE,
|
|
0,
|
|
pptable,
|
|
false);
|
|
}
|
|
|
|
void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev)
|
|
{
|
|
struct metrics_table_header *header = (struct metrics_table_header *)table;
|
|
uint16_t structure_size;
|
|
|
|
#define METRICS_VERSION(a, b) ((a << 16) | b )
|
|
|
|
switch (METRICS_VERSION(frev, crev)) {
|
|
case METRICS_VERSION(1, 0):
|
|
structure_size = sizeof(struct gpu_metrics_v1_0);
|
|
break;
|
|
case METRICS_VERSION(1, 1):
|
|
structure_size = sizeof(struct gpu_metrics_v1_1);
|
|
break;
|
|
case METRICS_VERSION(1, 2):
|
|
structure_size = sizeof(struct gpu_metrics_v1_2);
|
|
break;
|
|
case METRICS_VERSION(1, 3):
|
|
structure_size = sizeof(struct gpu_metrics_v1_3);
|
|
break;
|
|
case METRICS_VERSION(2, 0):
|
|
structure_size = sizeof(struct gpu_metrics_v2_0);
|
|
break;
|
|
case METRICS_VERSION(2, 1):
|
|
structure_size = sizeof(struct gpu_metrics_v2_1);
|
|
break;
|
|
case METRICS_VERSION(2, 2):
|
|
structure_size = sizeof(struct gpu_metrics_v2_2);
|
|
break;
|
|
case METRICS_VERSION(2, 3):
|
|
structure_size = sizeof(struct gpu_metrics_v2_3);
|
|
break;
|
|
default:
|
|
return;
|
|
}
|
|
|
|
#undef METRICS_VERSION
|
|
|
|
memset(header, 0xFF, structure_size);
|
|
|
|
header->format_revision = frev;
|
|
header->content_revision = crev;
|
|
header->structure_size = structure_size;
|
|
|
|
}
|
|
|
|
int smu_cmn_set_mp1_state(struct smu_context *smu,
|
|
enum pp_mp1_state mp1_state)
|
|
{
|
|
enum smu_message_type msg;
|
|
int ret;
|
|
|
|
switch (mp1_state) {
|
|
case PP_MP1_STATE_SHUTDOWN:
|
|
msg = SMU_MSG_PrepareMp1ForShutdown;
|
|
break;
|
|
case PP_MP1_STATE_UNLOAD:
|
|
msg = SMU_MSG_PrepareMp1ForUnload;
|
|
break;
|
|
case PP_MP1_STATE_RESET:
|
|
msg = SMU_MSG_PrepareMp1ForReset;
|
|
break;
|
|
case PP_MP1_STATE_NONE:
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
ret = smu_cmn_send_smc_msg(smu, msg, NULL);
|
|
if (ret)
|
|
dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
bool smu_cmn_is_audio_func_enabled(struct amdgpu_device *adev)
|
|
{
|
|
struct pci_dev *p = NULL;
|
|
bool snd_driver_loaded;
|
|
|
|
/*
|
|
* If the ASIC comes with no audio function, we always assume
|
|
* it is "enabled".
|
|
*/
|
|
p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
|
|
adev->pdev->bus->number, 1);
|
|
if (!p)
|
|
return true;
|
|
|
|
snd_driver_loaded = pci_is_enabled(p) ? true : false;
|
|
|
|
pci_dev_put(p);
|
|
|
|
return snd_driver_loaded;
|
|
}
|