243 lines
6.4 KiB
C
243 lines
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* eeprom specific definitions for mac80211 Prism54 drivers
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*
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* Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
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* Copyright (c) 2007-2009, Christian Lamparter <chunkeey@web.de>
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*
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* Based on:
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* - the islsm (softmac prism54) driver, which is:
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* Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
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*
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* - LMAC API interface header file for STLC4560 (lmac_longbow.h)
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* Copyright (C) 2007 Conexant Systems, Inc.
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*
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* - islmvc driver
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* Copyright (C) 2001 Intersil Americas Inc.
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*/
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#ifndef EEPROM_H
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#define EEPROM_H
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/* PDA defines are Copyright (C) 2005 Nokia Corporation (taken from islsm_pda.h) */
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struct pda_entry {
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__le16 len; /* includes both code and data */
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__le16 code;
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u8 data[];
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} __packed;
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struct eeprom_pda_wrap {
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__le32 magic;
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__le16 pad;
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__le16 len;
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__le32 arm_opcode;
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u8 data[];
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} __packed;
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struct p54_iq_autocal_entry {
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__le16 iq_param[4];
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} __packed;
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struct pda_iq_autocal_entry {
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__le16 freq;
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struct p54_iq_autocal_entry params;
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} __packed;
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struct pda_channel_output_limit {
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__le16 freq;
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u8 val_bpsk;
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u8 val_qpsk;
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u8 val_16qam;
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u8 val_64qam;
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u8 rate_set_mask;
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u8 rate_set_size;
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} __packed;
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struct pda_channel_output_limit_point_longbow {
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__le16 val_bpsk;
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__le16 val_qpsk;
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__le16 val_16qam;
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__le16 val_64qam;
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} __packed;
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struct pda_channel_output_limit_longbow {
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__le16 freq;
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struct pda_channel_output_limit_point_longbow point[3];
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} __packed;
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struct pda_pa_curve_data_sample_rev0 {
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u8 rf_power;
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u8 pa_detector;
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u8 pcv;
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} __packed;
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struct pda_pa_curve_data_sample_rev1 {
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u8 rf_power;
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u8 pa_detector;
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u8 data_barker;
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u8 data_bpsk;
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u8 data_qpsk;
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u8 data_16qam;
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u8 data_64qam;
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} __packed;
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struct pda_pa_curve_data {
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u8 cal_method_rev;
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u8 channels;
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u8 points_per_channel;
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u8 padding;
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u8 data[];
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} __packed;
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struct pda_rssi_cal_ext_entry {
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__le16 freq;
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__le16 mul;
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__le16 add;
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} __packed;
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struct pda_rssi_cal_entry {
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__le16 mul;
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__le16 add;
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} __packed;
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struct pda_country {
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u8 regdomain;
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u8 alpha2[2];
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u8 flags;
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} __packed;
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struct pda_antenna_gain {
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struct {
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u8 gain_5GHz; /* 0.25 dBi units */
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u8 gain_2GHz; /* 0.25 dBi units */
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} __packed antenna[0];
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} __packed;
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struct pda_custom_wrapper {
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__le16 entries;
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__le16 entry_size;
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__le16 offset;
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__le16 len;
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u8 data[];
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} __packed;
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/*
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* this defines the PDR codes used to build PDAs as defined in document
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* number 553155. The current implementation mirrors version 1.1 of the
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* document and lists only PDRs supported by the ARM platform.
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*/
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/* common and choice range (0x0000 - 0x0fff) */
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#define PDR_END 0x0000
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#define PDR_MANUFACTURING_PART_NUMBER 0x0001
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#define PDR_PDA_VERSION 0x0002
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#define PDR_NIC_SERIAL_NUMBER 0x0003
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#define PDR_NIC_RAM_SIZE 0x0005
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#define PDR_RFMODEM_SUP_RANGE 0x0006
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#define PDR_PRISM_MAC_SUP_RANGE 0x0007
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#define PDR_NIC_ID 0x0008
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#define PDR_MAC_ADDRESS 0x0101
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#define PDR_REGULATORY_DOMAIN_LIST 0x0103 /* obsolete */
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#define PDR_ALLOWED_CHAN_SET 0x0104
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#define PDR_DEFAULT_CHAN 0x0105
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#define PDR_TEMPERATURE_TYPE 0x0107
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#define PDR_IFR_SETTING 0x0200
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#define PDR_RFR_SETTING 0x0201
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#define PDR_3861_BASELINE_REG_SETTINGS 0x0202
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#define PDR_3861_SHADOW_REG_SETTINGS 0x0203
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#define PDR_3861_IFRF_REG_SETTINGS 0x0204
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#define PDR_3861_CHAN_CALIB_SET_POINTS 0x0300
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#define PDR_3861_CHAN_CALIB_INTEGRATOR 0x0301
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#define PDR_3842_PRISM_II_NIC_CONFIG 0x0400
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#define PDR_PRISM_USB_ID 0x0401
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#define PDR_PRISM_PCI_ID 0x0402
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#define PDR_PRISM_PCI_IF_CONFIG 0x0403
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#define PDR_PRISM_PCI_PM_CONFIG 0x0404
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#define PDR_3861_MF_TEST_CHAN_SET_POINTS 0x0900
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#define PDR_3861_MF_TEST_CHAN_INTEGRATORS 0x0901
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/* ARM range (0x1000 - 0x1fff) */
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#define PDR_COUNTRY_INFORMATION 0x1000 /* obsolete */
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#define PDR_INTERFACE_LIST 0x1001
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#define PDR_HARDWARE_PLATFORM_COMPONENT_ID 0x1002
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#define PDR_OEM_NAME 0x1003
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#define PDR_PRODUCT_NAME 0x1004
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#define PDR_UTF8_OEM_NAME 0x1005
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#define PDR_UTF8_PRODUCT_NAME 0x1006
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#define PDR_COUNTRY_LIST 0x1007
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#define PDR_DEFAULT_COUNTRY 0x1008
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#define PDR_ANTENNA_GAIN 0x1100
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#define PDR_PRISM_INDIGO_PA_CALIBRATION_DATA 0x1901
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#define PDR_RSSI_LINEAR_APPROXIMATION 0x1902
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#define PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS 0x1903
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#define PDR_PRISM_PA_CAL_CURVE_DATA 0x1904
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#define PDR_RSSI_LINEAR_APPROXIMATION_DUAL_BAND 0x1905
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#define PDR_PRISM_ZIF_TX_IQ_CALIBRATION 0x1906
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#define PDR_REGULATORY_POWER_LIMITS 0x1907
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#define PDR_RSSI_LINEAR_APPROXIMATION_EXTENDED 0x1908
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#define PDR_RADIATED_TRANSMISSION_CORRECTION 0x1909
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#define PDR_PRISM_TX_IQ_CALIBRATION 0x190a
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/* reserved range (0x2000 - 0x7fff) */
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/* customer range (0x8000 - 0xffff) */
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#define PDR_BASEBAND_REGISTERS 0x8000
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#define PDR_PER_CHANNEL_BASEBAND_REGISTERS 0x8001
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/* used by our modificated eeprom image */
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#define PDR_RSSI_LINEAR_APPROXIMATION_CUSTOM 0xDEAD
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#define PDR_RSSI_LINEAR_APPROXIMATION_CUSTOMV2 0xCAFF
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#define PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS_CUSTOM 0xBEEF
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#define PDR_PRISM_PA_CAL_CURVE_DATA_CUSTOM 0xB05D
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/* Interface Definitions */
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#define PDR_INTERFACE_ROLE_SERVER 0x0000
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#define PDR_INTERFACE_ROLE_CLIENT 0x0001
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/* PDR definitions for default country & country list */
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#define PDR_COUNTRY_CERT_CODE 0x80
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#define PDR_COUNTRY_CERT_CODE_REAL 0x00
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#define PDR_COUNTRY_CERT_CODE_PSEUDO 0x80
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#define PDR_COUNTRY_CERT_BAND 0x40
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#define PDR_COUNTRY_CERT_BAND_2GHZ 0x00
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#define PDR_COUNTRY_CERT_BAND_5GHZ 0x40
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#define PDR_COUNTRY_CERT_IODOOR 0x30
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#define PDR_COUNTRY_CERT_IODOOR_BOTH 0x00
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#define PDR_COUNTRY_CERT_IODOOR_INDOOR 0x20
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#define PDR_COUNTRY_CERT_IODOOR_OUTDOOR 0x30
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#define PDR_COUNTRY_CERT_INDEX 0x0f
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/* Specific LMAC FW/HW variant definitions */
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#define PDR_SYNTH_FRONTEND_MASK 0x0007
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#define PDR_SYNTH_FRONTEND_DUETTE3 0x0001
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#define PDR_SYNTH_FRONTEND_DUETTE2 0x0002
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#define PDR_SYNTH_FRONTEND_FRISBEE 0x0003
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#define PDR_SYNTH_FRONTEND_XBOW 0x0004
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#define PDR_SYNTH_FRONTEND_LONGBOW 0x0005
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#define PDR_SYNTH_IQ_CAL_MASK 0x0018
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#define PDR_SYNTH_IQ_CAL_PA_DETECTOR 0x0000
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#define PDR_SYNTH_IQ_CAL_DISABLED 0x0008
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#define PDR_SYNTH_IQ_CAL_ZIF 0x0010
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#define PDR_SYNTH_FAA_SWITCH_MASK 0x0020
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#define PDR_SYNTH_FAA_SWITCH_ENABLED 0x0020
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#define PDR_SYNTH_24_GHZ_MASK 0x0040
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#define PDR_SYNTH_24_GHZ_DISABLED 0x0040
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#define PDR_SYNTH_5_GHZ_MASK 0x0080
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#define PDR_SYNTH_5_GHZ_DISABLED 0x0080
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#define PDR_SYNTH_RX_DIV_MASK 0x0100
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#define PDR_SYNTH_RX_DIV_SUPPORTED 0x0100
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#define PDR_SYNTH_TX_DIV_MASK 0x0200
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#define PDR_SYNTH_TX_DIV_SUPPORTED 0x0200
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#define PDR_SYNTH_ASM_MASK 0x0400
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#define PDR_SYNTH_ASM_XSWON 0x0400
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#endif /* EEPROM_H */
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