451 lines
11 KiB
C
451 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/media-bus-format.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_graph.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <drm/drm_atomic_state_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_print.h>
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#define PC_CTRL_REG 0x0
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#define PC_COMBINE_ENABLE BIT(0)
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#define PC_DISP_BYPASS(n) BIT(1 + 21 * (n))
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#define PC_DISP_HSYNC_POLARITY(n) BIT(2 + 11 * (n))
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#define PC_DISP_HSYNC_POLARITY_POS(n) DISP_HSYNC_POLARITY(n)
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#define PC_DISP_VSYNC_POLARITY(n) BIT(3 + 11 * (n))
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#define PC_DISP_VSYNC_POLARITY_POS(n) DISP_VSYNC_POLARITY(n)
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#define PC_DISP_DVALID_POLARITY(n) BIT(4 + 11 * (n))
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#define PC_DISP_DVALID_POLARITY_POS(n) DISP_DVALID_POLARITY(n)
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#define PC_VSYNC_MASK_ENABLE BIT(5)
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#define PC_SKIP_MODE BIT(6)
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#define PC_SKIP_NUMBER_MASK GENMASK(12, 7)
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#define PC_SKIP_NUMBER(n) FIELD_PREP(PC_SKIP_NUMBER_MASK, (n))
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#define PC_DISP0_PIX_DATA_FORMAT_MASK GENMASK(18, 16)
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#define PC_DISP0_PIX_DATA_FORMAT(fmt) \
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FIELD_PREP(PC_DISP0_PIX_DATA_FORMAT_MASK, (fmt))
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#define PC_DISP1_PIX_DATA_FORMAT_MASK GENMASK(21, 19)
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#define PC_DISP1_PIX_DATA_FORMAT(fmt) \
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FIELD_PREP(PC_DISP1_PIX_DATA_FORMAT_MASK, (fmt))
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#define PC_SW_RESET_REG 0x20
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#define PC_SW_RESET_N BIT(0)
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#define PC_DISP_SW_RESET_N(n) BIT(1 + (n))
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#define PC_FULL_RESET_N (PC_SW_RESET_N | \
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PC_DISP_SW_RESET_N(0) | \
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PC_DISP_SW_RESET_N(1))
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#define PC_REG_SET 0x4
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#define PC_REG_CLR 0x8
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#define DRIVER_NAME "imx8qxp-pixel-combiner"
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enum imx8qxp_pc_pix_data_format {
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RGB,
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YUV444,
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YUV422,
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SPLIT_RGB,
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};
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struct imx8qxp_pc_channel {
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struct drm_bridge bridge;
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struct drm_bridge *next_bridge;
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struct imx8qxp_pc *pc;
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unsigned int stream_id;
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bool is_available;
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};
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struct imx8qxp_pc {
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struct device *dev;
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struct imx8qxp_pc_channel ch[2];
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struct clk *clk_apb;
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void __iomem *base;
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};
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static inline u32 imx8qxp_pc_read(struct imx8qxp_pc *pc, unsigned int offset)
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{
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return readl(pc->base + offset);
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}
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static inline void
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imx8qxp_pc_write(struct imx8qxp_pc *pc, unsigned int offset, u32 value)
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{
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writel(value, pc->base + offset);
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}
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static inline void
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imx8qxp_pc_write_set(struct imx8qxp_pc *pc, unsigned int offset, u32 value)
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{
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imx8qxp_pc_write(pc, offset + PC_REG_SET, value);
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}
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static inline void
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imx8qxp_pc_write_clr(struct imx8qxp_pc *pc, unsigned int offset, u32 value)
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{
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imx8qxp_pc_write(pc, offset + PC_REG_CLR, value);
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}
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static enum drm_mode_status
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imx8qxp_pc_bridge_mode_valid(struct drm_bridge *bridge,
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const struct drm_display_info *info,
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const struct drm_display_mode *mode)
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{
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if (mode->hdisplay > 2560)
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return MODE_BAD_HVALUE;
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return MODE_OK;
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}
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static int imx8qxp_pc_bridge_attach(struct drm_bridge *bridge,
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enum drm_bridge_attach_flags flags)
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{
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struct imx8qxp_pc_channel *ch = bridge->driver_private;
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struct imx8qxp_pc *pc = ch->pc;
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if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
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DRM_DEV_ERROR(pc->dev,
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"do not support creating a drm_connector\n");
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return -EINVAL;
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}
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if (!bridge->encoder) {
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DRM_DEV_ERROR(pc->dev, "missing encoder\n");
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return -ENODEV;
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}
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return drm_bridge_attach(bridge->encoder,
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ch->next_bridge, bridge,
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DRM_BRIDGE_ATTACH_NO_CONNECTOR);
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}
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static void
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imx8qxp_pc_bridge_mode_set(struct drm_bridge *bridge,
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const struct drm_display_mode *mode,
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const struct drm_display_mode *adjusted_mode)
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{
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struct imx8qxp_pc_channel *ch = bridge->driver_private;
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struct imx8qxp_pc *pc = ch->pc;
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u32 val;
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int ret;
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ret = pm_runtime_get_sync(pc->dev);
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if (ret < 0)
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DRM_DEV_ERROR(pc->dev,
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"failed to get runtime PM sync: %d\n", ret);
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ret = clk_prepare_enable(pc->clk_apb);
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if (ret)
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DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n",
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__func__, ret);
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/* HSYNC to pixel link is active low. */
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imx8qxp_pc_write_clr(pc, PC_CTRL_REG,
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PC_DISP_HSYNC_POLARITY(ch->stream_id));
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/* VSYNC to pixel link is active low. */
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imx8qxp_pc_write_clr(pc, PC_CTRL_REG,
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PC_DISP_VSYNC_POLARITY(ch->stream_id));
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/* Data enable to pixel link is active high. */
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imx8qxp_pc_write_set(pc, PC_CTRL_REG,
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PC_DISP_DVALID_POLARITY(ch->stream_id));
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/* Mask the first frame output which may be incomplete. */
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imx8qxp_pc_write_set(pc, PC_CTRL_REG, PC_VSYNC_MASK_ENABLE);
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/* Only support RGB currently. */
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val = imx8qxp_pc_read(pc, PC_CTRL_REG);
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if (ch->stream_id == 0) {
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val &= ~PC_DISP0_PIX_DATA_FORMAT_MASK;
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val |= PC_DISP0_PIX_DATA_FORMAT(RGB);
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} else {
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val &= ~PC_DISP1_PIX_DATA_FORMAT_MASK;
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val |= PC_DISP1_PIX_DATA_FORMAT(RGB);
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}
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imx8qxp_pc_write(pc, PC_CTRL_REG, val);
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/* Only support bypass mode currently. */
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imx8qxp_pc_write_set(pc, PC_CTRL_REG, PC_DISP_BYPASS(ch->stream_id));
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clk_disable_unprepare(pc->clk_apb);
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}
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static void
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imx8qxp_pc_bridge_atomic_disable(struct drm_bridge *bridge,
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struct drm_bridge_state *old_bridge_state)
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{
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struct imx8qxp_pc_channel *ch = bridge->driver_private;
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struct imx8qxp_pc *pc = ch->pc;
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int ret;
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ret = pm_runtime_put(pc->dev);
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if (ret < 0)
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DRM_DEV_ERROR(pc->dev, "failed to put runtime PM: %d\n", ret);
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}
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static const u32 imx8qxp_pc_bus_output_fmts[] = {
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MEDIA_BUS_FMT_RGB888_1X36_CPADLO,
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MEDIA_BUS_FMT_RGB666_1X36_CPADLO,
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};
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static bool imx8qxp_pc_bus_output_fmt_supported(u32 fmt)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(imx8qxp_pc_bus_output_fmts); i++) {
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if (imx8qxp_pc_bus_output_fmts[i] == fmt)
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return true;
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}
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return false;
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}
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static u32 *
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imx8qxp_pc_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
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struct drm_bridge_state *bridge_state,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state,
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u32 output_fmt,
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unsigned int *num_input_fmts)
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{
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u32 *input_fmts;
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if (!imx8qxp_pc_bus_output_fmt_supported(output_fmt))
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return NULL;
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*num_input_fmts = 1;
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input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL);
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if (!input_fmts)
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return NULL;
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switch (output_fmt) {
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case MEDIA_BUS_FMT_RGB888_1X36_CPADLO:
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input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X30_CPADLO;
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break;
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case MEDIA_BUS_FMT_RGB666_1X36_CPADLO:
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input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X30_CPADLO;
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break;
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default:
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kfree(input_fmts);
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input_fmts = NULL;
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break;
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}
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return input_fmts;
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}
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static u32 *
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imx8qxp_pc_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
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struct drm_bridge_state *bridge_state,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state,
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unsigned int *num_output_fmts)
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{
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*num_output_fmts = ARRAY_SIZE(imx8qxp_pc_bus_output_fmts);
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return kmemdup(imx8qxp_pc_bus_output_fmts,
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sizeof(imx8qxp_pc_bus_output_fmts), GFP_KERNEL);
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}
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static const struct drm_bridge_funcs imx8qxp_pc_bridge_funcs = {
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.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
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.atomic_reset = drm_atomic_helper_bridge_reset,
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.mode_valid = imx8qxp_pc_bridge_mode_valid,
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.attach = imx8qxp_pc_bridge_attach,
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.mode_set = imx8qxp_pc_bridge_mode_set,
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.atomic_disable = imx8qxp_pc_bridge_atomic_disable,
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.atomic_get_input_bus_fmts =
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imx8qxp_pc_bridge_atomic_get_input_bus_fmts,
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.atomic_get_output_bus_fmts =
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imx8qxp_pc_bridge_atomic_get_output_bus_fmts,
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};
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static int imx8qxp_pc_bridge_probe(struct platform_device *pdev)
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{
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struct imx8qxp_pc *pc;
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struct imx8qxp_pc_channel *ch;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct device_node *child, *remote;
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u32 i;
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int ret;
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pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
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if (!pc)
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return -ENOMEM;
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pc->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(pc->base))
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return PTR_ERR(pc->base);
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pc->dev = dev;
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pc->clk_apb = devm_clk_get(dev, "apb");
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if (IS_ERR(pc->clk_apb)) {
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ret = PTR_ERR(pc->clk_apb);
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if (ret != -EPROBE_DEFER)
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DRM_DEV_ERROR(dev, "failed to get apb clock: %d\n", ret);
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return ret;
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}
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platform_set_drvdata(pdev, pc);
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pm_runtime_enable(dev);
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for_each_available_child_of_node(np, child) {
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ret = of_property_read_u32(child, "reg", &i);
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if (ret || i > 1) {
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ret = -EINVAL;
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DRM_DEV_ERROR(dev,
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"invalid channel(%u) node address\n", i);
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goto free_child;
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}
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ch = &pc->ch[i];
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ch->pc = pc;
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ch->stream_id = i;
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remote = of_graph_get_remote_node(child, 1, 0);
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if (!remote) {
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ret = -ENODEV;
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DRM_DEV_ERROR(dev,
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"channel%u failed to get port1's remote node: %d\n",
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i, ret);
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goto free_child;
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}
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ch->next_bridge = of_drm_find_bridge(remote);
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if (!ch->next_bridge) {
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of_node_put(remote);
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ret = -EPROBE_DEFER;
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DRM_DEV_DEBUG_DRIVER(dev,
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"channel%u failed to find next bridge: %d\n",
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i, ret);
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goto free_child;
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}
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of_node_put(remote);
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ch->bridge.driver_private = ch;
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ch->bridge.funcs = &imx8qxp_pc_bridge_funcs;
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ch->bridge.of_node = child;
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ch->is_available = true;
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drm_bridge_add(&ch->bridge);
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}
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return 0;
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free_child:
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of_node_put(child);
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if (i == 1 && pc->ch[0].next_bridge)
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drm_bridge_remove(&pc->ch[0].bridge);
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pm_runtime_disable(dev);
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return ret;
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}
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static int imx8qxp_pc_bridge_remove(struct platform_device *pdev)
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{
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struct imx8qxp_pc *pc = platform_get_drvdata(pdev);
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struct imx8qxp_pc_channel *ch;
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int i;
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for (i = 0; i < 2; i++) {
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ch = &pc->ch[i];
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if (!ch->is_available)
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continue;
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drm_bridge_remove(&ch->bridge);
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ch->is_available = false;
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}
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pm_runtime_disable(&pdev->dev);
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return 0;
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}
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static int __maybe_unused imx8qxp_pc_runtime_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct imx8qxp_pc *pc = platform_get_drvdata(pdev);
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int ret;
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ret = clk_prepare_enable(pc->clk_apb);
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if (ret)
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DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n",
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__func__, ret);
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/* Disable pixel combiner by full reset. */
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imx8qxp_pc_write_clr(pc, PC_SW_RESET_REG, PC_FULL_RESET_N);
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clk_disable_unprepare(pc->clk_apb);
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/* Ensure the reset takes effect. */
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usleep_range(10, 20);
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return ret;
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}
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static int __maybe_unused imx8qxp_pc_runtime_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct imx8qxp_pc *pc = platform_get_drvdata(pdev);
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int ret;
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ret = clk_prepare_enable(pc->clk_apb);
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if (ret) {
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DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n",
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__func__, ret);
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return ret;
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}
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/* out of reset */
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imx8qxp_pc_write_set(pc, PC_SW_RESET_REG, PC_FULL_RESET_N);
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clk_disable_unprepare(pc->clk_apb);
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return ret;
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}
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static const struct dev_pm_ops imx8qxp_pc_pm_ops = {
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SET_RUNTIME_PM_OPS(imx8qxp_pc_runtime_suspend,
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imx8qxp_pc_runtime_resume, NULL)
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};
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static const struct of_device_id imx8qxp_pc_dt_ids[] = {
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{ .compatible = "fsl,imx8qm-pixel-combiner", },
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{ .compatible = "fsl,imx8qxp-pixel-combiner", },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx8qxp_pc_dt_ids);
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static struct platform_driver imx8qxp_pc_bridge_driver = {
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.probe = imx8qxp_pc_bridge_probe,
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.remove = imx8qxp_pc_bridge_remove,
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.driver = {
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.pm = &imx8qxp_pc_pm_ops,
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.name = DRIVER_NAME,
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.of_match_table = imx8qxp_pc_dt_ids,
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},
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};
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module_platform_driver(imx8qxp_pc_bridge_driver);
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MODULE_DESCRIPTION("i.MX8QM/QXP pixel combiner bridge driver");
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MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:" DRIVER_NAME);
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