127 lines
2.8 KiB
YAML
127 lines
2.8 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-hdmi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra HDMI Output Encoder
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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properties:
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$nodename:
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pattern: "^hdmi@[0-9a-f]+$"
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compatible:
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oneOf:
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- enum:
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- nvidia,tegra20-hdmi
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- nvidia,tegra30-hdmi
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- nvidia,tegra114-hdmi
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- nvidia,tegra124-hdmi
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- items:
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- const: nvidia,tegra132-hdmi
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- const: nvidia,tegra124-hdmi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: module clock
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- description: parent clock
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clock-names:
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items:
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- const: hdmi
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- const: parent
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resets:
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items:
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- description: module reset
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reset-names:
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items:
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- const: hdmi
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operating-points-v2:
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$ref: "/schemas/types.yaml#/definitions/phandle"
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power-domains:
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items:
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- description: phandle to the core power domain
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hdmi-supply:
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description: supply for the +5V HDMI connector pin
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vdd-supply:
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description: regulator for supply voltage
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pll-supply:
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description: regulator for PLL
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nvidia,ddc-i2c-bus:
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description: phandle of an I2C controller used for DDC EDID
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probing
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$ref: "/schemas/types.yaml#/definitions/phandle"
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nvidia,hpd-gpio:
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description: specifies a GPIO used for hotplug detection
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maxItems: 1
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nvidia,edid:
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description: supplies a binary EDID blob
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$ref: "/schemas/types.yaml#/definitions/uint8-array"
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nvidia,panel:
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description: phandle of a display panel
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$ref: "/schemas/types.yaml#/definitions/phandle"
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"#sound-dai-cells":
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const: 0
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additionalProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- resets
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- reset-names
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- pll-supply
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- vdd-supply
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- nvidia,ddc-i2c-bus
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- nvidia,hpd-gpio
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examples:
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- |
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#include <dt-bindings/clock/tegra124-car.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/tegra-gpio.h>
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hdmi@54280000 {
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compatible = "nvidia,tegra124-hdmi";
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reg = <0x54280000 0x00040000>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA124_CLK_HDMI>,
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<&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
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clock-names = "hdmi", "parent";
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resets = <&tegra_car 51>;
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reset-names = "hdmi";
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hdmi-supply = <&vdd_5v0_hdmi>;
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pll-supply = <&vdd_hdmi_pll>;
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vdd-supply = <&vdd_3v3_hdmi>;
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nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
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};
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