117 lines
3.0 KiB
YAML
117 lines
3.0 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek Display Port Controller
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maintainers:
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- Chun-Kuang Hu <chunkuang.hu@kernel.org>
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- Jitao shi <jitao.shi@mediatek.com>
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description: |
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MediaTek DP and eDP are different hardwares and there are some features
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which are not supported for eDP. For example, audio is not supported for
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eDP. Therefore, we need to use two different compatibles to describe them.
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In addition, We just need to enable the power domain of DP, so the clock
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of DP is generated by itself and we are not using other PLL to generate
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clocks.
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properties:
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compatible:
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enum:
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- mediatek,mt8195-dp-tx
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- mediatek,mt8195-edp-tx
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reg:
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maxItems: 1
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nvmem-cells:
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maxItems: 1
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description: efuse data for display port calibration
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nvmem-cell-names:
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const: dp_calibration_data
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power-domains:
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maxItems: 1
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interrupts:
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: Input endpoint of the controller, usually dp_intf
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port@1:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description: Output endpoint of the controller
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properties:
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endpoint:
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$ref: /schemas/media/video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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description: |
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number of lanes supported by the hardware.
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The possible values:
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0 - For 1 lane enabled in IP.
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0 1 - For 2 lanes enabled in IP.
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0 1 2 3 - For 4 lanes enabled in IP.
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minItems: 1
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maxItems: 4
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required:
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- data-lanes
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required:
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- port@0
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- port@1
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max-linkrate-mhz:
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enum: [ 1620, 2700, 5400, 8100 ]
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description: maximum link rate supported by the hardware.
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required:
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- compatible
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- reg
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- interrupts
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- ports
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- max-linkrate-mhz
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/mt8195-power.h>
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dptx@1c600000 {
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compatible = "mediatek,mt8195-dp-tx";
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reg = <0x1c600000 0x8000>;
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power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
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interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
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max-linkrate-mhz = <8100>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dptx_in: endpoint {
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remote-endpoint = <&dp_intf0_out>;
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};
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};
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port@1 {
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reg = <1>;
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dptx_out: endpoint {
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data-lanes = <0 1 2 3>;
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};
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};
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};
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};
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